mirror of
https://github.com/Ryujinx/Ryujinx.git
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Add some tests (#18)
* Add tests * Add some simple Alu instruction tests * travis: Run tests * CpuTest: Add TearDown
This commit is contained in:
Merry
gdkchan
parent
1df2c5ce7f
commit
1bfe6a9c22
10 changed files with 164 additions and 2 deletions
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@ -6,3 +6,4 @@ dotnet: 2.0.0
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script:
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- dotnet restore
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- dotnet build
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- cd Ryujinx.Tests && dotnet test
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73
Ryujinx.Tests/Cpu/CpuTest.cs
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73
Ryujinx.Tests/Cpu/CpuTest.cs
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@ -0,0 +1,73 @@
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using ChocolArm64;
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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using NUnit.Framework;
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using System;
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using System.Runtime.InteropServices;
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using System.Threading;
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namespace Ryujinx.Tests.Cpu
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{
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[TestFixture]
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public partial class CpuTest
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{
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IntPtr Ram;
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AMemoryAlloc Allocator;
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AMemory Memory;
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[SetUp]
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public void Setup()
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{
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Ram = Marshal.AllocHGlobal((IntPtr)AMemoryMgr.RamSize);
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Allocator = new AMemoryAlloc();
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Memory = new AMemory(Ram, Allocator);
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Memory.Manager.MapPhys(0x1000, 0x1000, 2, AMemoryPerm.Read | AMemoryPerm.Write | AMemoryPerm.Execute);
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}
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[TearDown]
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public void Teardown()
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{
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Marshal.FreeHGlobal(Ram);
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}
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private void Execute(AThread Thread)
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{
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AutoResetEvent Wait = new AutoResetEvent(false);
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Thread.Registers.Break += (sender, e) => Thread.StopExecution();
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Thread.WorkFinished += (sender, e) => Wait.Set();
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Wait.Reset();
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Thread.Execute();
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Wait.WaitOne();
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}
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private ARegisters SingleOpcode(uint Opcode,
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ulong X0 = 0, ulong X1 = 0, ulong X2 = 0,
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AVec V0 = new AVec(), AVec V1 = new AVec(), AVec V2 = new AVec())
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{
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Memory.WriteUInt32(0x1000, Opcode);
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Memory.WriteUInt32(0x1004, 0xD4200000); // BRK #0
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Memory.WriteUInt32(0x1008, 0xD65F03C0); // RET
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AThread Thread = new AThread(Memory, ThreadPriority.Normal, 0x1000);
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Thread.Registers.X0 = X0;
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Thread.Registers.X1 = X1;
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Thread.Registers.X2 = X2;
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Thread.Registers.V0 = V0;
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Thread.Registers.V1 = V1;
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Thread.Registers.V2 = V2;
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Execute(Thread);
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return Thread.Registers;
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}
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[Test]
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public void SanityCheck()
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{
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uint Opcode = 0xD503201F; // NOP
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Assert.AreEqual(SingleOpcode(Opcode, X0: 0).X0, 0);
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Assert.AreEqual(SingleOpcode(Opcode, X0: 1).X0, 1);
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Assert.AreEqual(SingleOpcode(Opcode, X0: 2).X0, 2);
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Assert.AreEqual(SingleOpcode(Opcode, X0: 42).X0, 42);
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}
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}
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}
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65
Ryujinx.Tests/Cpu/CpuTestAlu.cs
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65
Ryujinx.Tests/Cpu/CpuTestAlu.cs
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@ -0,0 +1,65 @@
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[TestFixture]
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public partial class CpuTest
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{
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[Test]
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public void Add()
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{
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// ADD X0, X1, X2
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ARegisters Registers = SingleOpcode(0x8B020020, X1: 1, X2: 2);
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Assert.AreEqual(3, Registers.X0);
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}
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[Test]
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public void Ands()
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{
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// ANDS W0, W1, W2
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uint Opcode = 0x6A020020;
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var tests = new[]
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{
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new { W1 = 0xFFFFFFFFul, W2 = 0xFFFFFFFFul, Result = 0xFFFFFFFFul, Negative = true, Zero = false },
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new { W1 = 0xFFFFFFFFul, W2 = 0x00000000ul, Result = 0x00000000ul, Negative = false, Zero = true },
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new { W1 = 0x12345678ul, W2 = 0x7324A993ul, Result = 0x12240010ul, Negative = false, Zero = false },
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};
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foreach (var test in tests)
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{
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ARegisters Registers = SingleOpcode(Opcode, X1: test.W1, X2: test.W2);
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Assert.AreEqual(test.Result, Registers.X0);
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Assert.AreEqual(test.Negative, Registers.Negative);
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Assert.AreEqual(test.Zero, Registers.Zero);
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}
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}
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[Test]
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public void OrrBitmasks()
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{
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// ORR W0, WZR, #0x01010101
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Assert.AreEqual(0x01010101, SingleOpcode(0x3200C3E0).X0);
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// ORR W1, WZR, #0x00F000F0
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Assert.AreEqual(0x00F000F0, SingleOpcode(0x320C8FE1).X1);
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// ORR W2, WZR, #1
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Assert.AreEqual(0x00000001, SingleOpcode(0x320003E2).X2);
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}
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[Test]
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public void RevX0X0()
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{
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// REV X0, X0
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ARegisters Registers = SingleOpcode(0xDAC00C00, X0: 0xAABBCCDDEEFF1100);
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Assert.AreEqual(0x0011FFEEDDCCBBAA, Registers.X0);
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}
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[Test]
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public void RevW1W1()
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{
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// REV W1, W1
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ARegisters Registers = SingleOpcode(0x5AC00821, X1: 0x12345678);
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Assert.AreEqual(0x78563412, Registers.X1);
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}
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}
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}
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17
Ryujinx.Tests/Ryujinx.Tests.csproj
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17
Ryujinx.Tests/Ryujinx.Tests.csproj
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@ -0,0 +1,17 @@
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<Project Sdk="Microsoft.NET.Sdk">
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<PropertyGroup>
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<TargetFramework>netcoreapp2.0</TargetFramework>
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<IsPackable>false</IsPackable>
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</PropertyGroup>
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<PropertyGroup>
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<GenerateAssemblyInfo>false</GenerateAssemblyInfo>
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</PropertyGroup>
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<ItemGroup>
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<PackageReference Include="Microsoft.NET.Test.Sdk" Version="15.3.0-preview-20170628-02" />
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<PackageReference Include="NUnit" Version="3.9.0" />
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<PackageReference Include="NUnit3TestAdapter" Version="3.9.0" />
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</ItemGroup>
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<ItemGroup>
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<ProjectReference Include="..\Ryujinx\Ryujinx.csproj" />
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</ItemGroup>
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</Project>
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@ -3,7 +3,9 @@ Microsoft Visual Studio Solution File, Format Version 12.00
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# Visual Studio 15
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VisualStudioVersion = 15.0.26730.8
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MinimumVisualStudioVersion = 10.0.40219.1
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Project("{9A19103F-16F7-4668-BE54-9A1E7A4F7556}") = "Ryujinx", "Ryujinx.csproj", "{074045D4-3ED2-4711-9169-E385F2BFB5A0}"
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Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "Ryujinx", "Ryujinx\Ryujinx.csproj", "{074045D4-3ED2-4711-9169-E385F2BFB5A0}"
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EndProject
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Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "Ryujinx.Tests", "Ryujinx.Tests\Ryujinx.Tests.csproj", "{EBB55AEA-C7D7-4DEB-BF96-FA1789E225E9}"
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EndProject
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Global
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GlobalSection(SolutionConfigurationPlatforms) = preSolution
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@ -15,6 +17,10 @@ Global
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{074045D4-3ED2-4711-9169-E385F2BFB5A0}.Debug|Any CPU.Build.0 = Debug|Any CPU
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{074045D4-3ED2-4711-9169-E385F2BFB5A0}.Release|Any CPU.ActiveCfg = Release|Any CPU
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{074045D4-3ED2-4711-9169-E385F2BFB5A0}.Release|Any CPU.Build.0 = Release|Any CPU
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{EBB55AEA-C7D7-4DEB-BF96-FA1789E225E9}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
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{EBB55AEA-C7D7-4DEB-BF96-FA1789E225E9}.Debug|Any CPU.Build.0 = Debug|Any CPU
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{EBB55AEA-C7D7-4DEB-BF96-FA1789E225E9}.Release|Any CPU.ActiveCfg = Release|Any CPU
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{EBB55AEA-C7D7-4DEB-BF96-FA1789E225E9}.Release|Any CPU.Build.0 = Release|Any CPU
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EndGlobalSection
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GlobalSection(SolutionProperties) = preSolution
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HideSolutionNode = FALSE
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@ -5,7 +5,7 @@ using System.Threading;
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namespace ChocolArm64
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{
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class AThread
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public class AThread
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{
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public ARegisters Registers { get; private set; }
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public AMemory Memory { get; private set; }
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