mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-10-01 12:30:00 +02:00
Fix Fmin/max and add vector version, add and modifying fmin/max tests (#89)
This commit is contained in:
MS-DOS1999
gdkchan
parent
6e69cd9284
commit
76a5972378
5 changed files with 250 additions and 20 deletions
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@ -211,8 +211,10 @@ namespace ChocolArm64
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Set("0>1011100<1xxxxx111111xxxxxxxxxx", AInstEmit.Fdiv_V, typeof(AOpCodeSimdReg));
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Set("000111110x0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Fmadd_S, typeof(AOpCodeSimdReg));
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Set("000111100x1xxxxx010010xxxxxxxxxx", AInstEmit.Fmax_S, typeof(AOpCodeSimdReg));
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Set("0x0011100x1xxxxx111101xxxxxxxxxx", AInstEmit.Fmax_V, typeof(AOpCodeSimdReg));
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Set("000111100x1xxxxx011010xxxxxxxxxx", AInstEmit.Fmaxnm_S, typeof(AOpCodeSimdReg));
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Set("000111100x1xxxxx010110xxxxxxxxxx", AInstEmit.Fmin_S, typeof(AOpCodeSimdReg));
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Set("0x0011101x1xxxxx111101xxxxxxxxxx", AInstEmit.Fmin_V, typeof(AOpCodeSimdReg));
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Set("000111100x1xxxxx011110xxxxxxxxxx", AInstEmit.Fminnm_S, typeof(AOpCodeSimdReg));
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Set("0>0011100<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmla_V, typeof(AOpCodeSimdReg));
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Set("0x0011111<<xxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Ve, typeof(AOpCodeSimdRegElemF));
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@ -211,17 +211,87 @@ namespace ChocolArm64.Instruction
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public static void Fmax_S(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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EmitScalarBinaryOpF(Context, () =>
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{
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EmitBinaryMathCall(Context, nameof(Math.Max));
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if (Op.Size == 0)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.MaxF));
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}
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else if (Op.Size == 1)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Max));
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}
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else
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{
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throw new InvalidOperationException();
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}
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});
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}
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public static void Fmax_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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EmitVectorBinaryOpF(Context, () =>
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{
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if (Op.Size == 0)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.MaxF));
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}
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else if (Op.Size == 1)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Max));
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}
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else
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{
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throw new InvalidOperationException();
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}
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});
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}
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public static void Fmin_S(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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EmitScalarBinaryOpF(Context, () =>
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{
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EmitBinaryMathCall(Context, nameof(Math.Min));
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if (Op.Size == 0)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.MinF));
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}
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else if (Op.Size == 1)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Min));
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}
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else
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{
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throw new InvalidOperationException();
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}
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});
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}
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public static void Fmin_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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EmitVectorBinaryOpF(Context, () =>
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{
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if (SizeF == 0)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.MinF));
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}
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else if (SizeF == 1)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Min));
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}
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else
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{
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throw new InvalidOperationException();
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}
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});
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}
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@ -510,17 +580,19 @@ namespace ChocolArm64.Instruction
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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EmitVectorUnaryOpF(Context, () =>
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{
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Context.EmitLdarg(ATranslatedSub.StateArgIdx);
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Context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Fpcr));
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if (Op.Size == 2)
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if (SizeF == 0)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.RoundF));
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}
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else if (Op.Size == 3)
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else if (SizeF == 1)
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{
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ASoftFallback.EmitCall(Context, nameof(ASoftFallback.Round));
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}
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@ -256,6 +256,82 @@ namespace ChocolArm64.Instruction
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((Value >> 6) & 1) + (Value >> 7);
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}
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public static float MaxF(float val1, float val2)
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{
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if (val1 == 0.0 && val2 == 0.0)
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{
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if (BitConverter.SingleToInt32Bits(val1) < 0 && BitConverter.SingleToInt32Bits(val2) < 0)
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return -0.0f;
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return 0.0f;
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}
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if (val1 > val2)
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return val1;
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if (float.IsNaN(val1))
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return val1;
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return val2;
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}
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public static double Max(double val1, double val2)
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{
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if (val1 == 0.0 && val2 == 0.0)
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{
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if (BitConverter.DoubleToInt64Bits(val1) < 0 && BitConverter.DoubleToInt64Bits(val2) < 0)
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return -0.0;
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return 0.0;
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}
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if (val1 > val2)
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return val1;
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if (double.IsNaN(val1))
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return val1;
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return val2;
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}
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public static float MinF(float val1, float val2)
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{
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if (val1 == 0.0 && val2 == 0.0)
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{
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if (BitConverter.SingleToInt32Bits(val1) < 0 || BitConverter.SingleToInt32Bits(val2) < 0)
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return -0.0f;
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return 0.0f;
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}
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if (val1 < val2)
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return val1;
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if (float.IsNaN(val1))
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return val1;
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return val2;
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}
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public static double Min(double val1, double val2)
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{
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if (val1 == 0.0 && val2 == 0.0)
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{
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if (BitConverter.DoubleToInt64Bits(val1) < 0 || BitConverter.DoubleToInt64Bits(val2) < 0)
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return -0.0;
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return 0.0;
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}
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if (val1 < val2)
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return val1;
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if (double.IsNaN(val1))
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return val1;
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return val2;
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}
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public static float RoundF(float Value, int Fpcr)
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{
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switch ((ARoundMode)((Fpcr >> 22) & 3))
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@ -5,24 +5,52 @@ namespace Ryujinx.Tests.Cpu
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{
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public class CpuTestScalar : CpuTest
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{
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[TestCase(0x00000000u, 0x80000000u, 0x00000000u)]
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[TestCase(0x80000000u, 0x00000000u, 0x00000000u)]
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[TestCase(0x80000000u, 0x80000000u, 0x80000000u)]
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[TestCase(0x3DCCCCCDu, 0x3C9623B1u, 0x3DCCCCCDu)]
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[TestCase(0x8BA98D27u, 0x00000076u, 0x00000076u)]
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[TestCase(0x807FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu)]
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[TestCase(0x7F7FFFFFu, 0x807FFFFFu, 0x7F7FFFFFu)]
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[TestCase(0x7FC00000u, 0x3F800000u, 0x7FC00000u)]
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[TestCase(0x3F800000u, 0x7FC00000u, 0x7FC00000u)]
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[TestCase(0x7F800001u, 0x7FC00042u, 0x7FC00001u, Ignore = "NaN test.")]
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[TestCase(0x7FC00042u, 0x7F800001u, 0x7FC00001u, Ignore = "NaN test.")]
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[TestCase(0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Au, Ignore = "NaN test.")]
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public void Fmax_S(uint A, uint B, uint Result)
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[TestCase(0x1E224820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000000000000ul)]
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[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000000000000ul)]
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[TestCase(0x1E224820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
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[TestCase(0x1E224820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x000000003DCCCCCDul)]
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[TestCase(0x1E224820u, 0x000000003DCCCCCDul, 0x000000003C9623B1ul, 0x000000003DCCCCCDul)]
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[TestCase(0x1E224820u, 0x000000008BA98D27ul, 0x0000000000000076ul, 0x0000000000000076ul)]
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[TestCase(0x1E224820u, 0x00000000807FFFFFul, 0x000000007F7FFFFFul, 0x000000007F7FFFFFul)]
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[TestCase(0x1E224820u, 0x000000007F7FFFFFul, 0x00000000807FFFFFul, 0x000000007F7FFFFFul)]
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[TestCase(0x1E224820u, 0x000000007FC00000ul, 0x000000003F800000ul, 0x000000007FC00000ul)]
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[TestCase(0x1E224820u, 0x000000003F800000ul, 0x000000007FC00000ul, 0x000000007FC00000ul)]
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[TestCase(0x1E224820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
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[TestCase(0x1E224820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
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[TestCase(0x1E224820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul, Ignore = "NaN test.")]
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[TestCase(0x1E624820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x0000000000000000ul)]
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[TestCase(0x1E624820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x0000000000000000ul)]
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[TestCase(0x1E624820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
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[TestCase(0x1E624820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x3FF3333333333333ul)]
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public void Fmax_S(uint Opcode, ulong A, ulong B, ulong Result)
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{
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// FMAX S0, S1, S2
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uint Opcode = 0x1E224820;
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AThreadState ThreadState = SingleOpcode(Opcode, V1: new AVec { W0 = A }, V2: new AVec { W0 = B });
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Assert.AreEqual(Result, ThreadState.V0.W0);
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AThreadState ThreadState = SingleOpcode(Opcode, V1: new AVec { X0 = A }, V2: new AVec { X0 = B });
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Assert.AreEqual(Result, ThreadState.V0.X0);
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}
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[TestCase(0x1E225820u, 0x0000000000000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
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[TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000000000000ul, 0x0000000080000000ul)]
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[TestCase(0x1E225820u, 0x0000000080000000ul, 0x0000000080000000ul, 0x0000000080000000ul)]
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[TestCase(0x1E225820u, 0x0000000080000000ul, 0x000000003DCCCCCDul, 0x0000000080000000ul)]
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[TestCase(0x1E225820u, 0x000000003DCCCCCDul, 0x000000003C9623B1ul, 0x000000003C9623B1ul)]
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[TestCase(0x1E225820u, 0x000000008BA98D27ul, 0x0000000000000076ul, 0x000000008BA98D27ul)]
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[TestCase(0x1E225820u, 0x00000000807FFFFFul, 0x000000007F7FFFFFul, 0x00000000807FFFFFul)]
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[TestCase(0x1E225820u, 0x000000007F7FFFFFul, 0x00000000807FFFFFul, 0x00000000807FFFFFul)]
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[TestCase(0x1E225820u, 0x000000007FC00000ul, 0x000000003F800000ul, 0x000000007FC00000ul)]
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[TestCase(0x1E225820u, 0x000000003F800000ul, 0x000000007FC00000ul, 0x000000007FC00000ul)]
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[TestCase(0x1E225820u, 0x000000007F800001ul, 0x000000007FC00042ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
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[TestCase(0x1E225820u, 0x000000007FC00042ul, 0x000000007F800001ul, 0x000000007FC00001ul, Ignore = "NaN test.")]
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[TestCase(0x1E225820u, 0x000000007FC0000Aul, 0x000000007FC0000Bul, 0x000000007FC0000Aul, Ignore = "NaN test.")]
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[TestCase(0x1E625820u, 0x0000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
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[TestCase(0x1E625820u, 0x8000000000000000ul, 0x0000000000000000ul, 0x8000000000000000ul)]
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[TestCase(0x1E625820u, 0x8000000000000000ul, 0x8000000000000000ul, 0x8000000000000000ul)]
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[TestCase(0x1E625820u, 0x8000000000000000ul, 0x3FF3333333333333ul, 0x8000000000000000ul)]
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public void Fmin_S(uint Opcode, ulong A, ulong B, ulong Result)
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{
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// FMIN S0, S1, S2
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AThreadState ThreadState = SingleOpcode(Opcode, V1: new AVec { X0 = A }, V2: new AVec { X0 = B });
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Assert.AreEqual(Result, ThreadState.V0.X0);
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}
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}
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}
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@ -45,6 +45,58 @@ namespace Ryujinx.Tests.Cpu
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});
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}
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[TestCase(0x80000000u, 0x80000000u, 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u)]
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[TestCase(0x00000000u, 0x00000000u, 0x80000000u, 0x80000000u, 0x00000000u, 0x00000000u)]
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[TestCase(0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u)]
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[TestCase(0x80000000u, 0x80000000u, 0x3DCCCCCDu, 0x3DCCCCCDu, 0x3DCCCCCDu, 0x3DCCCCCDu)]
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[TestCase(0x3DCCCCCDu, 0x3DCCCCCDu, 0x3C9623B1u, 0x3C9623B1u, 0x3DCCCCCDu, 0x3DCCCCCDu)]
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[TestCase(0x8BA98D27u, 0x8BA98D27u, 0x00000076u, 0x00000076u, 0x00000076u, 0x00000076u)]
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[TestCase(0x807FFFFFu, 0x807FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu)]
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[TestCase(0x7F7FFFFFu, 0x7F7FFFFFu, 0x807FFFFFu, 0x807FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu)]
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[TestCase(0x7FC00000u, 0x7FC00000u, 0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u)]
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[TestCase(0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u)]
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[TestCase(0x7F800001u, 0x7F800001u, 0x7FC00042u, 0x7FC00042u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")]
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[TestCase(0x7FC00042u, 0x7FC00042u, 0x7F800001u, 0x7F800001u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")]
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[TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au, Ignore = "NaN test.")]
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public void Fmax_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1)
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{
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uint Opcode = 0x4E22F420;
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AVec V1 = new AVec { X0 = A, X1 = B };
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AVec V2 = new AVec { X0 = C, X1 = D };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(Result0, ThreadState.V0.X0);
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Assert.AreEqual(Result1, ThreadState.V0.X1);
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});
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}
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[TestCase(0x80000000u, 0x80000000u, 0x00000000u, 0x00000000u, 0x80000000u, 0x80000000u)]
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[TestCase(0x00000000u, 0x00000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u)]
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[TestCase(0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u, 0x80000000u)]
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[TestCase(0x80000000u, 0x80000000u, 0x3DCCCCCDu, 0x3DCCCCCDu, 0x80000000u, 0x80000000u)]
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[TestCase(0x3DCCCCCDu, 0x3DCCCCCDu, 0x3C9623B1u, 0x3C9623B1u, 0x3C9623B1u, 0x3C9623B1u)]
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[TestCase(0x8BA98D27u, 0x8BA98D27u, 0x00000076u, 0x00000076u, 0x8BA98D27u, 0x8BA98D27u)]
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[TestCase(0x807FFFFFu, 0x807FFFFFu, 0x7F7FFFFFu, 0x7F7FFFFFu, 0x807FFFFFu, 0x807FFFFFu)]
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[TestCase(0x7F7FFFFFu, 0x7F7FFFFFu, 0x807FFFFFu, 0x807FFFFFu, 0x807FFFFFu, 0x807FFFFFu)]
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[TestCase(0x7FC00000u, 0x7FC00000u, 0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u)]
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[TestCase(0x3F800000u, 0x3F800000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u, 0x7FC00000u)]
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[TestCase(0x7F800001u, 0x7F800001u, 0x7FC00042u, 0x7FC00042u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")]
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[TestCase(0x7FC00042u, 0x7FC00042u, 0x7F800001u, 0x7F800001u, 0x7FC00001u, 0x7FC00001u, Ignore = "NaN test.")]
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[TestCase(0x7FC0000Au, 0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Bu, 0x7FC0000Au, 0x7FC0000Au, Ignore = "NaN test.")]
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public void Fmin_V(uint A, uint B, uint C, uint D, uint Result0, uint Result1)
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{
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uint Opcode = 0x4EA2F420;
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AVec V1 = new AVec { X0 = A, X1 = B };
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AVec V2 = new AVec { X0 = C, X1 = D };
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AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
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Assert.Multiple(() =>
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{
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Assert.AreEqual(Result0, ThreadState.V0.X0);
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Assert.AreEqual(Result1, ThreadState.V0.X1);
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});
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}
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[Test, Description("fmul s6, s1, v0.s[2]")]
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public void Fmul_Se([Random(10)] float A, [Random(10)] float B)
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{
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