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Arm64: Cpu feature detection (#4264)
* Arm64: Cpu feature detection * Ptc: Add Arm64 feature info * nits * simplify CheckSysctlName * restore some macos flags * feedback
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4 changed files with 237 additions and 31 deletions
185
ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs
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185
ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs
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@ -0,0 +1,185 @@
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using System;
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using System.Linq;
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using System.Reflection;
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using System.Runtime.CompilerServices;
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using System.Runtime.InteropServices;
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using System.Runtime.Intrinsics.Arm;
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using System.Runtime.Versioning;
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namespace ARMeilleure.CodeGen.Arm64
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{
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static partial class HardwareCapabilities
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{
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static HardwareCapabilities()
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{
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if (!ArmBase.Arm64.IsSupported)
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{
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return;
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}
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if (OperatingSystem.IsLinux())
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{
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LinuxFeatureInfoHwCap = (LinuxFeatureFlagsHwCap)getauxval(AT_HWCAP);
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LinuxFeatureInfoHwCap2 = (LinuxFeatureFlagsHwCap2)getauxval(AT_HWCAP2);
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}
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if (OperatingSystem.IsMacOS())
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{
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for (int i = 0; i < _sysctlNames.Length; i++)
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{
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if (CheckSysctlName(_sysctlNames[i]))
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{
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MacOsFeatureInfo |= (MacOsFeatureFlags)(1 << i);
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}
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}
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}
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}
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#region Linux
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private const ulong AT_HWCAP = 16;
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private const ulong AT_HWCAP2 = 26;
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[LibraryImport("libc", SetLastError = true)]
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private static partial ulong getauxval(ulong type);
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[Flags]
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public enum LinuxFeatureFlagsHwCap : ulong
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{
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Fp = 1 << 0,
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Asimd = 1 << 1,
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Evtstrm = 1 << 2,
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Aes = 1 << 3,
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Pmull = 1 << 4,
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Sha1 = 1 << 5,
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Sha2 = 1 << 6,
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Crc32 = 1 << 7,
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Atomics = 1 << 8,
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FpHp = 1 << 9,
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AsimdHp = 1 << 10,
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CpuId = 1 << 11,
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AsimdRdm = 1 << 12,
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Jscvt = 1 << 13,
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Fcma = 1 << 14,
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Lrcpc = 1 << 15,
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DcpOp = 1 << 16,
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Sha3 = 1 << 17,
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Sm3 = 1 << 18,
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Sm4 = 1 << 19,
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AsimdDp = 1 << 20,
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Sha512 = 1 << 21,
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Sve = 1 << 22,
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AsimdFhm = 1 << 23,
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Dit = 1 << 24,
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Uscat = 1 << 25,
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Ilrcpc = 1 << 26,
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FlagM = 1 << 27,
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Ssbs = 1 << 28,
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Sb = 1 << 29,
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Paca = 1 << 30,
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Pacg = 1UL << 31
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}
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[Flags]
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public enum LinuxFeatureFlagsHwCap2 : ulong
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{
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Dcpodp = 1 << 0,
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Sve2 = 1 << 1,
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SveAes = 1 << 2,
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SvePmull = 1 << 3,
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SveBitperm = 1 << 4,
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SveSha3 = 1 << 5,
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SveSm4 = 1 << 6,
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FlagM2 = 1 << 7,
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Frint = 1 << 8,
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SveI8mm = 1 << 9,
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SveF32mm = 1 << 10,
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SveF64mm = 1 << 11,
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SveBf16 = 1 << 12,
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I8mm = 1 << 13,
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Bf16 = 1 << 14,
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Dgh = 1 << 15,
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Rng = 1 << 16,
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Bti = 1 << 17,
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Mte = 1 << 18,
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Ecv = 1 << 19,
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Afp = 1 << 20,
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Rpres = 1 << 21,
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Mte3 = 1 << 22,
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Sme = 1 << 23,
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Sme_i16i64 = 1 << 24,
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Sme_f64f64 = 1 << 25,
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Sme_i8i32 = 1 << 26,
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Sme_f16f32 = 1 << 27,
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Sme_b16f32 = 1 << 28,
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Sme_f32f32 = 1 << 29,
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Sme_fa64 = 1 << 30,
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Wfxt = 1UL << 31,
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Ebf16 = 1UL << 32,
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Sve_Ebf16 = 1UL << 33,
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Cssc = 1UL << 34,
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Rprfm = 1UL << 35,
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Sve2p1 = 1UL << 36
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}
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public static LinuxFeatureFlagsHwCap LinuxFeatureInfoHwCap { get; } = 0;
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public static LinuxFeatureFlagsHwCap2 LinuxFeatureInfoHwCap2 { get; } = 0;
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#endregion
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#region macOS
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[LibraryImport("libSystem.dylib", SetLastError = true)]
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private static unsafe partial int sysctlbyname([MarshalAs(UnmanagedType.LPStr)] string name, out int oldValue, ref ulong oldSize, IntPtr newValue, ulong newValueSize);
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[SupportedOSPlatform("macos")]
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private static bool CheckSysctlName(string name)
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{
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ulong size = sizeof(int);
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if (sysctlbyname(name, out int val, ref size, IntPtr.Zero, 0) == 0 && size == sizeof(int))
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{
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return val != 0;
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}
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return false;
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}
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private static string[] _sysctlNames = new string[]
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{
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"hw.optional.floatingpoint",
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"hw.optional.AdvSIMD",
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"hw.optional.arm.FEAT_FP16",
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"hw.optional.arm.FEAT_AES",
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"hw.optional.arm.FEAT_PMULL",
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"hw.optional.arm.FEAT_LSE",
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"hw.optional.armv8_crc32",
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"hw.optional.arm.FEAT_SHA1",
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"hw.optional.arm.FEAT_SHA256"
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};
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[Flags]
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public enum MacOsFeatureFlags
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{
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Fp = 1 << 0,
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AdvSimd = 1 << 1,
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Fp16 = 1 << 2,
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Aes = 1 << 3,
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Pmull = 1 << 4,
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Lse = 1 << 5,
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Crc32 = 1 << 6,
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Sha1 = 1 << 7,
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Sha256 = 1 << 8
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}
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public static MacOsFeatureFlags MacOsFeatureInfo { get; } = 0;
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#endregion
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public static bool SupportsAdvSimd => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Asimd) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.AdvSimd);
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public static bool SupportsAes => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Aes) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.Aes);
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public static bool SupportsPmull => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Pmull) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.Pmull);
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public static bool SupportsLse => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Atomics) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.Lse);
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public static bool SupportsCrc32 => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Crc32) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.Crc32);
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public static bool SupportsSha1 => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Sha1) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.Sha1);
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public static bool SupportsSha256 => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Sha2) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.Sha256);
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}
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}
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@ -2556,7 +2556,7 @@ namespace ARMeilleure.Instructions
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{
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OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp;
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if (Optimizations.UseAdvSimd && false) // Not supported by all Arm CPUs.
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if (Optimizations.UseArm64Pmull)
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{
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InstEmitSimdHelperArm64.EmitVectorBinaryOp(context, Intrinsic.Arm64PmullV);
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}
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@ -1,8 +1,10 @@
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using ARMeilleure.CodeGen.X86;
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using System.Runtime.Intrinsics.Arm;
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namespace ARMeilleure
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{
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using Arm64HardwareCapabilities = ARMeilleure.CodeGen.Arm64.HardwareCapabilities;
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using X86HardwareCapabilities = ARMeilleure.CodeGen.X86.HardwareCapabilities;
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public static class Optimizations
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{
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public static bool FastFP { get; set; } = true;
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@ -10,7 +12,8 @@ namespace ARMeilleure
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public static bool AllowLcqInFunctionTable { get; set; } = true;
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public static bool UseUnmanagedDispatchLoop { get; set; } = true;
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public static bool UseAdvSimdIfAvailable { get; set; } = true;
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public static bool UseAdvSimdIfAvailable { get; set; } = true;
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public static bool UseArm64PmullIfAvailable { get; set; } = true;
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public static bool UseSseIfAvailable { get; set; } = true;
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public static bool UseSse2IfAvailable { get; set; } = true;
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@ -29,25 +32,26 @@ namespace ARMeilleure
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public static bool ForceLegacySse
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{
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get => HardwareCapabilities.ForceLegacySse;
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set => HardwareCapabilities.ForceLegacySse = value;
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get => X86HardwareCapabilities.ForceLegacySse;
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set => X86HardwareCapabilities.ForceLegacySse = value;
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}
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internal static bool UseAdvSimd => UseAdvSimdIfAvailable && AdvSimd.IsSupported;
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internal static bool UseAdvSimd => UseAdvSimdIfAvailable && Arm64HardwareCapabilities.SupportsAdvSimd;
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internal static bool UseArm64Pmull => UseArm64PmullIfAvailable && Arm64HardwareCapabilities.SupportsPmull;
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internal static bool UseSse => UseSseIfAvailable && HardwareCapabilities.SupportsSse;
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internal static bool UseSse2 => UseSse2IfAvailable && HardwareCapabilities.SupportsSse2;
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internal static bool UseSse3 => UseSse3IfAvailable && HardwareCapabilities.SupportsSse3;
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internal static bool UseSsse3 => UseSsse3IfAvailable && HardwareCapabilities.SupportsSsse3;
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internal static bool UseSse41 => UseSse41IfAvailable && HardwareCapabilities.SupportsSse41;
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internal static bool UseSse42 => UseSse42IfAvailable && HardwareCapabilities.SupportsSse42;
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internal static bool UsePopCnt => UsePopCntIfAvailable && HardwareCapabilities.SupportsPopcnt;
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internal static bool UseAvx => UseAvxIfAvailable && HardwareCapabilities.SupportsAvx && !ForceLegacySse;
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internal static bool UseF16c => UseF16cIfAvailable && HardwareCapabilities.SupportsF16c;
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internal static bool UseFma => UseFmaIfAvailable && HardwareCapabilities.SupportsFma;
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internal static bool UseAesni => UseAesniIfAvailable && HardwareCapabilities.SupportsAesni;
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internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && HardwareCapabilities.SupportsPclmulqdq;
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internal static bool UseSha => UseShaIfAvailable && HardwareCapabilities.SupportsSha;
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internal static bool UseGfni => UseGfniIfAvailable && HardwareCapabilities.SupportsGfni;
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internal static bool UseSse => UseSseIfAvailable && X86HardwareCapabilities.SupportsSse;
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internal static bool UseSse2 => UseSse2IfAvailable && X86HardwareCapabilities.SupportsSse2;
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internal static bool UseSse3 => UseSse3IfAvailable && X86HardwareCapabilities.SupportsSse3;
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internal static bool UseSsse3 => UseSsse3IfAvailable && X86HardwareCapabilities.SupportsSsse3;
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internal static bool UseSse41 => UseSse41IfAvailable && X86HardwareCapabilities.SupportsSse41;
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internal static bool UseSse42 => UseSse42IfAvailable && X86HardwareCapabilities.SupportsSse42;
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internal static bool UsePopCnt => UsePopCntIfAvailable && X86HardwareCapabilities.SupportsPopcnt;
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internal static bool UseAvx => UseAvxIfAvailable && X86HardwareCapabilities.SupportsAvx && !ForceLegacySse;
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internal static bool UseF16c => UseF16cIfAvailable && X86HardwareCapabilities.SupportsF16c;
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internal static bool UseFma => UseFmaIfAvailable && X86HardwareCapabilities.SupportsFma;
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internal static bool UseAesni => UseAesniIfAvailable && X86HardwareCapabilities.SupportsAesni;
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internal static bool UsePclmulqdq => UsePclmulqdqIfAvailable && X86HardwareCapabilities.SupportsPclmulqdq;
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internal static bool UseSha => UseShaIfAvailable && X86HardwareCapabilities.SupportsSha;
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internal static bool UseGfni => UseGfniIfAvailable && X86HardwareCapabilities.SupportsGfni;
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}
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}
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}
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@ -1,7 +1,6 @@
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using ARMeilleure.CodeGen;
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using ARMeilleure.CodeGen.Linking;
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using ARMeilleure.CodeGen.Unwinding;
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using ARMeilleure.CodeGen.X86;
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using ARMeilleure.Common;
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using ARMeilleure.Memory;
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using Ryujinx.Common;
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@ -22,12 +21,15 @@ using static ARMeilleure.Translation.PTC.PtcFormatter;
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namespace ARMeilleure.Translation.PTC
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{
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using Arm64HardwareCapabilities = ARMeilleure.CodeGen.Arm64.HardwareCapabilities;
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using X86HardwareCapabilities = ARMeilleure.CodeGen.X86.HardwareCapabilities;
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class Ptc : IPtcLoadState
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{
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private const string OuterHeaderMagicString = "PTCohd\0\0";
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private const string InnerHeaderMagicString = "PTCihd\0\0";
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private const uint InternalVersion = 4114; //! To be incremented manually for each change to the ARMeilleure project.
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private const uint InternalVersion = 4264; //! To be incremented manually for each change to the ARMeilleure project.
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private const string ActualDir = "0";
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private const string BackupDir = "1";
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@ -952,11 +954,26 @@ namespace ARMeilleure.Translation.PTC
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private static FeatureInfo GetFeatureInfo()
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{
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return new FeatureInfo(
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(uint)HardwareCapabilities.FeatureInfo1Ecx,
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(uint)HardwareCapabilities.FeatureInfo1Edx,
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(uint)HardwareCapabilities.FeatureInfo7Ebx,
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(uint)HardwareCapabilities.FeatureInfo7Ecx);
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if (RuntimeInformation.ProcessArchitecture == Architecture.Arm64)
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{
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return new FeatureInfo(
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(ulong)Arm64HardwareCapabilities.LinuxFeatureInfoHwCap,
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(ulong)Arm64HardwareCapabilities.LinuxFeatureInfoHwCap2,
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(ulong)Arm64HardwareCapabilities.MacOsFeatureInfo,
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0);
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}
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else if (RuntimeInformation.ProcessArchitecture == Architecture.X64)
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{
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return new FeatureInfo(
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(ulong)X86HardwareCapabilities.FeatureInfo1Ecx,
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(ulong)X86HardwareCapabilities.FeatureInfo1Edx,
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(ulong)X86HardwareCapabilities.FeatureInfo7Ebx,
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(ulong)X86HardwareCapabilities.FeatureInfo7Ecx);
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}
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else
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{
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return new FeatureInfo(0, 0, 0, 0);
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}
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}
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private byte GetMemoryManagerMode()
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@ -976,7 +993,7 @@ namespace ARMeilleure.Translation.PTC
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return osPlatform;
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}
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[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 58*/)]
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[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 74*/)]
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private struct OuterHeader
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{
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public ulong Magic;
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@ -1007,8 +1024,8 @@ namespace ARMeilleure.Translation.PTC
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}
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}
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[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 16*/)]
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private record struct FeatureInfo(uint FeatureInfo0, uint FeatureInfo1, uint FeatureInfo2, uint FeatureInfo3);
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[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 32*/)]
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private record struct FeatureInfo(ulong FeatureInfo0, ulong FeatureInfo1, ulong FeatureInfo2, ulong FeatureInfo3);
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[StructLayout(LayoutKind.Sequential, Pack = 1/*, Size = 128*/)]
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private struct InnerHeader
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