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Implement ATOM shader instruction (#1687)
* Implement ATOM shader instruction * Fix reduction type decoding
This commit is contained in:
parent
934a78005e
commit
c3d62bd078
5 changed files with 45 additions and 22 deletions
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@ -10,6 +10,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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BitwiseAnd = 5,
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BitwiseAnd = 5,
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BitwiseOr = 6,
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BitwiseOr = 6,
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BitwiseExclusiveOr = 7,
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BitwiseExclusiveOr = 7,
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Swap = 8
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Swap = 8,
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SafeAdd = 10 // Only supported by ATOM.
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}
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}
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}
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}
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@ -8,10 +8,6 @@ namespace Ryujinx.Graphics.Shader.Decoders
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public Register Ra { get; }
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public Register Ra { get; }
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public Register Rb { get; }
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public Register Rb { get; }
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public ReductionType Type { get; }
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public int Offset { get; }
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public bool Extended { get; }
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public bool Extended { get; }
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public AtomicOp AtomicOp { get; }
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public AtomicOp AtomicOp { get; }
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@ -24,15 +20,6 @@ namespace Ryujinx.Graphics.Shader.Decoders
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Ra = new Register(opCode.Extract(8, 8), RegisterType.Gpr);
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Ra = new Register(opCode.Extract(8, 8), RegisterType.Gpr);
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Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr);
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Rb = new Register(opCode.Extract(20, 8), RegisterType.Gpr);
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Type = (ReductionType)opCode.Extract(28, 2);
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if (Type == ReductionType.FP32FtzRn)
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{
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Type = ReductionType.S64;
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}
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Offset = opCode.Extract(30, 22);
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Extended = opCode.Extract(48);
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Extended = opCode.Extract(48);
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AtomicOp = (AtomicOp)opCode.Extract(52, 4);
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AtomicOp = (AtomicOp)opCode.Extract(52, 4);
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@ -34,6 +34,7 @@ namespace Ryujinx.Graphics.Shader.Decoders
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#region Instructions
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#region Instructions
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Set("1110111111011x", InstEmit.Ald, OpCodeAttribute.Create);
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Set("1110111111011x", InstEmit.Ald, OpCodeAttribute.Create);
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Set("1110111111110x", InstEmit.Ast, OpCodeAttribute.Create);
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Set("1110111111110x", InstEmit.Ast, OpCodeAttribute.Create);
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Set("11101101xxxxxx", InstEmit.Atom, OpCodeAtom.Create);
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Set("11101100xxxxxx", InstEmit.Atoms, OpCodeAtom.Create);
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Set("11101100xxxxxx", InstEmit.Atoms, OpCodeAtom.Create);
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Set("1111000010101x", InstEmit.Bar, OpCodeBarrier.Create);
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Set("1111000010101x", InstEmit.Bar, OpCodeBarrier.Create);
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Set("0100110000000x", InstEmit.Bfe, OpCodeAluCbuf.Create);
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Set("0100110000000x", InstEmit.Bfe, OpCodeAluCbuf.Create);
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@ -2,11 +2,11 @@ namespace Ryujinx.Graphics.Shader.Decoders
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{
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{
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enum ReductionType
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enum ReductionType
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{
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{
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U32 = 0,
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U32 = 0,
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S32 = 1,
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S32 = 1,
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U64 = 2,
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U64 = 2,
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FP32FtzRn = 3,
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FP32FtzRn = 3,
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U128 = 4,
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FP16x2FtzRn = 4,
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S64 = 5
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S64 = 5
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}
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}
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}
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}
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@ -57,13 +57,47 @@ namespace Ryujinx.Graphics.Shader.Instructions
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}
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}
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}
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}
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public static void Atom(EmitterContext context)
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{
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OpCodeAtom op = (OpCodeAtom)context.CurrOp;
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ReductionType type = (ReductionType)op.RawOpCode.Extract(49, 2);
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int sOffset = (op.RawOpCode.Extract(28, 20) << 12) >> 12;
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(Operand addrLow, Operand addrHigh) = Get40BitsAddress(context, op.Ra, op.Extended, sOffset);
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Operand value = GetSrcB(context);
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Operand res = EmitAtomicOp(
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context,
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Instruction.MrGlobal,
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op.AtomicOp,
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type,
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addrLow,
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addrHigh,
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value);
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context.Copy(GetDest(context), res);
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}
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public static void Atoms(EmitterContext context)
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public static void Atoms(EmitterContext context)
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{
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{
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OpCodeAtom op = (OpCodeAtom)context.CurrOp;
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OpCodeAtom op = (OpCodeAtom)context.CurrOp;
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ReductionType type = op.RawOpCode.Extract(28, 2) switch
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{
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0 => ReductionType.U32,
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1 => ReductionType.S32,
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2 => ReductionType.U64,
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_ => ReductionType.S64
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};
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Operand offset = context.ShiftRightU32(GetSrcA(context), Const(2));
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Operand offset = context.ShiftRightU32(GetSrcA(context), Const(2));
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offset = context.IAdd(offset, Const(op.Offset));
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int sOffset = (op.RawOpCode.Extract(30, 22) << 10) >> 10;
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offset = context.IAdd(offset, Const(sOffset));
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Operand value = GetSrcB(context);
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Operand value = GetSrcB(context);
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@ -71,7 +105,7 @@ namespace Ryujinx.Graphics.Shader.Instructions
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context,
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context,
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Instruction.MrShared,
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Instruction.MrShared,
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op.AtomicOp,
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op.AtomicOp,
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op.Type,
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type,
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offset,
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offset,
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Const(0),
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Const(0),
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value);
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value);
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