mirrors/Ryujinx
mirrors/Ryujinx
1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-10-01 12:30:00 +02:00
Code Wiki Activity

InstEmitMemory32: Literal loads always have word-aligned PC (#3104)

Browse source
This commit is contained in:
merry 2022-02-11 20:51:03 +00:00 committed by GitHub
parent f861f0bca2
commit ce71f9144e
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
2 changed files with 15 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
ARMeilleure/Instructions/InstEmitHelper.cs
View file

@ -47,6 +47,20 @@ namespace ARMeilleure.Instructions
} }
} }
public static Operand GetIntA32AlignedPC(ArmEmitterContext context, int regIndex)
{
if (regIndex == RegisterAlias.Aarch32Pc)
{
OpCode32 op = (OpCode32)context.CurrOp;
return Const((int)(op.GetPc() & 0xfffffffc));
}
else
{
return Register(GetRegisterAlias(context.Mode, regIndex), RegisterType.Integer, OperandType.I32);
}
}
public static Operand GetVecA32(int regIndex) public static Operand GetVecA32(int regIndex)
{ {
return Register(regIndex, RegisterType.Vector, OperandType.V128); return Register(regIndex, RegisterType.Vector, OperandType.V128);

2
ARMeilleure/Instructions/InstEmitMemory32.cs
View file

@ -153,7 +153,7 @@ namespace ARMeilleure.Instructions
{ {
OpCode32Mem op = (OpCode32Mem)context.CurrOp; OpCode32Mem op = (OpCode32Mem)context.CurrOp;
Operand n = context.Copy(GetIntA32(context, op.Rn)); Operand n = context.Copy(GetIntA32AlignedPC(context, op.Rn));
Operand m = GetMemM(context, setCarry: false); Operand m = GetMemM(context, setCarry: false);
Operand temp = default; Operand temp = default;