mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-10-01 12:30:00 +02:00
Use a new approach for shader BRX targets (#2532)
* Use a new approach for shader BRX targets * Make shader cache actually work * Improve the shader pattern matching a bit * Extend LDC search to predecessor blocks, catches more cases * Nit * Only save the amount of constant buffer data actually used. Avoids crashes on partially mapped buffers * Ignore Rd on predicate instructions, as they do not have a Rd register (catches more cases)
This commit is contained in:
parent
70f79e689b
commit
d9d18439f6
12 changed files with 472 additions and 149 deletions
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@ -38,6 +38,11 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
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/// </summary>
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RemoveManifestEntries,
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/// <summary>
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/// Remove entries from the hash manifest and save it, and also deletes the temporary file.
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/// </summary>
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RemoveManifestEntryAndTempFile,
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/// <summary>
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/// Flush temporary cache to archive.
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/// </summary>
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@ -116,6 +121,9 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
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/// </summary>
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private ZipArchive _cacheArchive;
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/// <summary>
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/// Indicates if the cache collection supports modification.
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/// </summary>
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public bool IsReadOnly { get; }
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/// <summary>
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@ -264,6 +272,21 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
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}
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}
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/// <summary>
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/// Remove given entry from the manifest and delete the temporary file.
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/// </summary>
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/// <param name="entry">Entry to remove from the manifest</param>
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private void RemoveManifestEntryAndTempFile(Hash128 entry)
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{
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lock (_hashTable)
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{
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_hashTable.Remove(entry);
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SaveManifest();
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}
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File.Delete(GenCacheTempFilePath(entry));
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}
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/// <summary>
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/// Queue a task to flush temporary files to the archive on the worker.
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/// </summary>
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@ -440,6 +463,9 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
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case CacheFileOperation.RemoveManifestEntries:
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RemoveManifestEntries((HashSet<Hash128>)task.Data);
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break;
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case CacheFileOperation.RemoveManifestEntryAndTempFile:
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RemoveManifestEntryAndTempFile((Hash128)task.Data);
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break;
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case CacheFileOperation.FlushToArchive:
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FlushToArchive();
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break;
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@ -472,7 +498,7 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
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{
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if (IsReadOnly)
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{
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Logger.Warning?.Print(LogClass.Gpu, "Trying to add {keyHash} on a read-only cache, ignoring.");
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Logger.Warning?.Print(LogClass.Gpu, $"Trying to add {keyHash} on a read-only cache, ignoring.");
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return;
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}
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@ -521,7 +547,7 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
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{
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if (IsReadOnly)
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{
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Logger.Warning?.Print(LogClass.Gpu, "Trying to replace {keyHash} on a read-only cache, ignoring.");
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Logger.Warning?.Print(LogClass.Gpu, $"Trying to replace {keyHash} on a read-only cache, ignoring.");
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return;
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}
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@ -540,6 +566,27 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
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});
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}
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/// <summary>
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/// Removes a value at the given hash from the cache.
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/// </summary>
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/// <param name="keyHash">The hash of the value in the cache</param>
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public void RemoveValue(ref Hash128 keyHash)
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{
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if (IsReadOnly)
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{
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Logger.Warning?.Print(LogClass.Gpu, $"Trying to remove {keyHash} on a read-only cache, ignoring.");
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return;
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}
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// Only queue file change operations
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_fileWriterWorkerQueue.Add(new CacheFileOperationTask
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{
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Type = CacheFileOperation.RemoveManifestEntryAndTempFile,
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Data = keyHash
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});
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}
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public void Dispose()
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{
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Dispose(true);
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@ -371,11 +371,13 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
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/// <summary>
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/// Create guest shader cache entries from the runtime contexts.
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/// </summary>
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/// <param name="memoryManager">The GPU memory manager in use</param>
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/// <param name="channel">The GPU channel in use</param>
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/// <param name="shaderContexts">The runtime contexts</param>
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/// <returns>Guest shader cahe entries from the runtime contexts</returns>
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public static GuestShaderCacheEntry[] CreateShaderCacheEntries(MemoryManager memoryManager, ReadOnlySpan<TranslatorContext> shaderContexts)
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public static GuestShaderCacheEntry[] CreateShaderCacheEntries(GpuChannel channel, ReadOnlySpan<TranslatorContext> shaderContexts)
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{
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MemoryManager memoryManager = channel.MemoryManager;
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int startIndex = shaderContexts.Length > 1 ? 1 : 0;
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GuestShaderCacheEntry[] entries = new GuestShaderCacheEntry[shaderContexts.Length - startIndex];
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@ -389,31 +391,66 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
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continue;
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}
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GpuAccessor gpuAccessor = context.GpuAccessor as GpuAccessor;
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ulong cb1DataAddress;
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int cb1DataSize = gpuAccessor?.Cb1DataSize ?? 0;
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if (context.Stage == ShaderStage.Compute)
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{
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cb1DataAddress = channel.BufferManager.GetComputeUniformBufferAddress(1);
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}
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else
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{
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int stageIndex = context.Stage switch
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{
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ShaderStage.TessellationControl => 1,
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ShaderStage.TessellationEvaluation => 2,
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ShaderStage.Geometry => 3,
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ShaderStage.Fragment => 4,
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_ => 0
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};
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cb1DataAddress = channel.BufferManager.GetGraphicsUniformBufferAddress(stageIndex, 1);
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}
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int size = context.Size;
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TranslatorContext translatorContext2 = i == 1 ? shaderContexts[0] : null;
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int sizeA = translatorContext2 != null ? translatorContext2.Size : 0;
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byte[] code = new byte[context.Size + sizeA];
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byte[] code = new byte[size + cb1DataSize + sizeA];
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memoryManager.GetSpan(context.Address, context.Size).CopyTo(code);
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memoryManager.GetSpan(context.Address, size).CopyTo(code);
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if (cb1DataAddress != 0 && cb1DataSize != 0)
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{
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memoryManager.Physical.GetSpan(cb1DataAddress, cb1DataSize).CopyTo(code.AsSpan().Slice(size, cb1DataSize));
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}
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if (translatorContext2 != null)
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{
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memoryManager.GetSpan(translatorContext2.Address, sizeA).CopyTo(code.AsSpan().Slice(context.Size, sizeA));
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memoryManager.GetSpan(translatorContext2.Address, sizeA).CopyTo(code.AsSpan().Slice(size + cb1DataSize, sizeA));
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}
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GuestGpuAccessorHeader gpuAccessorHeader = CreateGuestGpuAccessorCache(context.GpuAccessor);
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if (context.GpuAccessor is GpuAccessor)
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if (gpuAccessor != null)
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{
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gpuAccessorHeader.TextureDescriptorCount = context.TextureHandlesForCache.Count;
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}
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GuestShaderCacheEntryHeader header = new GuestShaderCacheEntryHeader(context.Stage, context.Size, sizeA, gpuAccessorHeader);
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GuestShaderCacheEntryHeader header = new GuestShaderCacheEntryHeader(
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context.Stage,
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size + cb1DataSize,
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sizeA,
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cb1DataSize,
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gpuAccessorHeader);
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GuestShaderCacheEntry entry = new GuestShaderCacheEntry(header, code);
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if (context.GpuAccessor is GpuAccessor gpuAccessor)
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if (gpuAccessor != null)
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{
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foreach (int textureHandle in context.TextureHandlesForCache)
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{
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@ -114,6 +114,16 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache
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_hostProgramCache.ReplaceValue(ref programCodeHash, data);
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}
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/// <summary>
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/// Removes a shader program present in the program cache.
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/// </summary>
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/// <param name="programCodeHash">Target program code hash</param>
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public void RemoveProgram(ref Hash128 programCodeHash)
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{
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_guestProgramCache.RemoveValue(ref programCodeHash);
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_hostProgramCache.RemoveValue(ref programCodeHash);
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}
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/// <summary>
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/// Get all guest program hashes.
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/// </summary>
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@ -40,9 +40,9 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache.Definition
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public int SizeA;
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/// <summary>
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/// Unused/reserved.
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/// Constant buffer 1 data size.
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/// </summary>
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public int Reserved4;
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public int Cb1DataSize;
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/// <summary>
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/// The header of the cached gpu accessor.
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@ -55,12 +55,14 @@ namespace Ryujinx.Graphics.Gpu.Shader.Cache.Definition
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/// <param name="stage">The stage of this shader</param>
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/// <param name="size">The size of the code section</param>
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/// <param name="sizeA">The size of the code2 section if present (Vertex A)</param>
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/// <param name="cb1DataSize">Constant buffer 1 data size</param>
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/// <param name="gpuAccessorHeader">The header of the cached gpu accessor</param>
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public GuestShaderCacheEntryHeader(ShaderStage stage, int size, int sizeA, GuestGpuAccessorHeader gpuAccessorHeader) : this()
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public GuestShaderCacheEntryHeader(ShaderStage stage, int size, int sizeA, int cb1DataSize, GuestGpuAccessorHeader gpuAccessorHeader) : this()
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{
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Stage = stage;
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Size = size;
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Size = size;
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SizeA = sizeA;
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Cb1DataSize = cb1DataSize;
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GpuAccessorHeader = gpuAccessorHeader;
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}
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}
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@ -11,6 +11,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
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{
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private readonly GpuContext _context;
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private readonly ReadOnlyMemory<byte> _data;
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private readonly ReadOnlyMemory<byte> _cb1Data;
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private readonly GuestGpuAccessorHeader _header;
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private readonly Dictionary<int, GuestTextureDescriptor> _textureDescriptors;
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@ -19,12 +20,19 @@ namespace Ryujinx.Graphics.Gpu.Shader
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/// </summary>
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/// <param name="context">GPU context</param>
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/// <param name="data">The data of the shader</param>
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/// <param name="cb1Data">The constant buffer 1 data of the shader</param>
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/// <param name="header">The cache of the GPU accessor</param>
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/// <param name="guestTextureDescriptors">The cache of the texture descriptors</param>
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public CachedGpuAccessor(GpuContext context, ReadOnlyMemory<byte> data, GuestGpuAccessorHeader header, Dictionary<int, GuestTextureDescriptor> guestTextureDescriptors)
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public CachedGpuAccessor(
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GpuContext context,
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ReadOnlyMemory<byte> data,
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ReadOnlyMemory<byte> cb1Data,
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GuestGpuAccessorHeader header,
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Dictionary<int, GuestTextureDescriptor> guestTextureDescriptors)
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{
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_context = context;
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_data = data;
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_cb1Data = cb1Data;
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_header = header;
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_textureDescriptors = new Dictionary<int, GuestTextureDescriptor>();
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}
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}
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/// <summary>
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/// Reads data from the constant buffer 1.
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/// </summary>
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/// <param name="offset">Offset in bytes to read from</param>
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/// <returns>Value at the given offset</returns>
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public uint ConstantBuffer1Read(int offset)
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{
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return MemoryMarshal.Cast<byte, uint>(_cb1Data.Span.Slice(offset))[0];
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}
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/// <summary>
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/// Prints a log message.
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/// </summary>
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@ -20,6 +20,8 @@ namespace Ryujinx.Graphics.Gpu.Shader
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private readonly int _localMemorySize;
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private readonly int _sharedMemorySize;
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public int Cb1DataSize { get; private set; }
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/// <summary>
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/// Creates a new instance of the GPU state accessor for graphics shader translation.
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/// </summary>
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@ -67,6 +69,25 @@ namespace Ryujinx.Graphics.Gpu.Shader
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_sharedMemorySize = sharedMemorySize;
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}
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/// <summary>
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/// Reads data from the constant buffer 1.
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/// </summary>
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/// <param name="offset">Offset in bytes to read from</param>
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/// <returns>Value at the given offset</returns>
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public uint ConstantBuffer1Read(int offset)
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{
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if (Cb1DataSize < offset + 4)
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{
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Cb1DataSize = offset + 4;
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}
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ulong baseAddress = _compute
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? _channel.BufferManager.GetComputeUniformBufferAddress(1)
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: _channel.BufferManager.GetGraphicsUniformBufferAddress(_stageIndex, 1);
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return _channel.MemoryManager.Physical.Read<uint>(baseAddress + (ulong)offset);
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}
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/// <summary>
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/// Prints a log message.
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/// </summary>
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@ -38,7 +38,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
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/// <summary>
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/// Version of the codegen (to be changed when codegen or guest format change).
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/// </summary>
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private const ulong ShaderCodeGenVersion = 2469;
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private const ulong ShaderCodeGenVersion = 2530;
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// Progress reporting helpers
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private volatile int _shaderCount;
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@ -112,7 +112,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
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int programIndex = 0;
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List<ShaderCompileTask> activeTasks = new List<ShaderCompileTask>();
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AutoResetEvent taskDoneEvent = new AutoResetEvent(false);
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using AutoResetEvent taskDoneEvent = new AutoResetEvent(false);
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// This thread dispatches tasks to do shader translation, and creates programs that OpenGL will link in the background.
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// The program link status is checked in a non-blocking manner so that multiple shaders can be compiled at once.
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@ -191,7 +191,14 @@ namespace Ryujinx.Graphics.Gpu.Shader
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Task compileTask = Task.Run(() =>
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{
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IGpuAccessor gpuAccessor = new CachedGpuAccessor(_context, entry.Code, entry.Header.GpuAccessorHeader, entry.TextureDescriptors);
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var binaryCode = new Memory<byte>(entry.Code);
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var gpuAccessor = new CachedGpuAccessor(
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_context,
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binaryCode,
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binaryCode.Slice(binaryCode.Length - entry.Header.Cb1DataSize),
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entry.Header.GpuAccessorHeader,
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entry.TextureDescriptors);
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var options = new TranslationOptions(TargetLanguage.Glsl, TargetApi.OpenGL, DefaultFlags | TranslationFlags.Compute);
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program = Translator.CreateContext(0, gpuAccessor, options).Translate(out shaderProgramInfo);
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@ -199,12 +206,20 @@ namespace Ryujinx.Graphics.Gpu.Shader
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task.OnTask(compileTask, (bool _, ShaderCompileTask task) =>
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{
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if (task.IsFaulted)
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{
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Logger.Warning?.Print(LogClass.Gpu, $"Host shader {key} is corrupted or incompatible, discarding...");
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_cacheManager.RemoveProgram(ref key);
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return true; // Exit early, the decoding step failed.
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}
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ShaderCodeHolder shader = new ShaderCodeHolder(program, shaderProgramInfo, entry.Code);
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Logger.Info?.Print(LogClass.Gpu, $"Host shader {key} got invalidated, rebuilding from guest...");
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// Compile shader and create program as the shader program binary got invalidated.
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shader.HostShader = _context.Renderer.CompileShader(ShaderStage.Compute, shader.Program.Code);
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shader.HostShader = _context.Renderer.CompileShader(ShaderStage.Compute, program.Code);
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hostProgram = _context.Renderer.CreateProgram(new IShader[] { shader.HostShader }, null);
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task.OnCompiled(hostProgram, (bool isNewProgramValid, ShaderCompileTask task) =>
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@ -298,7 +313,14 @@ namespace Ryujinx.Graphics.Gpu.Shader
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}
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else
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{
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IGpuAccessor gpuAccessor = new CachedGpuAccessor(_context, entry.Code, entry.Header.GpuAccessorHeader, entry.TextureDescriptors);
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var binaryCode = new Memory<byte>(entry.Code);
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var gpuAccessor = new CachedGpuAccessor(
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_context,
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binaryCode,
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binaryCode.Slice(binaryCode.Length - entry.Header.Cb1DataSize),
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entry.Header.GpuAccessorHeader,
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entry.TextureDescriptors);
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var options = new TranslationOptions(TargetLanguage.Glsl, TargetApi.OpenGL, flags);
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var options2 = new TranslationOptions(TargetLanguage.Glsl, TargetApi.OpenGL, flags | TranslationFlags.VertexA);
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|
@ -310,7 +332,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
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}
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// NOTE: Vertex B comes first in the shader cache.
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byte[] code = entry.Code.AsSpan().Slice(0, entry.Header.Size).ToArray();
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byte[] code = entry.Code.AsSpan().Slice(0, entry.Header.Size - entry.Header.Cb1DataSize).ToArray();
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byte[] code2 = entry.Code.AsSpan().Slice(entry.Header.Size, entry.Header.SizeA).ToArray();
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shaders[i] = new ShaderCodeHolder(program, shaderProgramInfo, code, code2);
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|
@ -326,13 +348,22 @@ namespace Ryujinx.Graphics.Gpu.Shader
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}
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else
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{
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IGpuAccessor gpuAccessor = new CachedGpuAccessor(_context, entry.Code, entry.Header.GpuAccessorHeader, entry.TextureDescriptors);
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var binaryCode = new Memory<byte>(entry.Code);
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var gpuAccessor = new CachedGpuAccessor(
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_context,
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binaryCode,
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binaryCode.Slice(binaryCode.Length - entry.Header.Cb1DataSize),
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entry.Header.GpuAccessorHeader,
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entry.TextureDescriptors);
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var options = new TranslationOptions(TargetLanguage.Glsl, TargetApi.OpenGL, flags);
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program = Translator.CreateContext(0, gpuAccessor, options, counts).Translate(out shaderProgramInfo);
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}
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shaders[i] = new ShaderCodeHolder(program, shaderProgramInfo, entry.Code);
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byte[] code = entry.Code.AsSpan().Slice(0, entry.Header.Size - entry.Header.Cb1DataSize).ToArray();
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shaders[i] = new ShaderCodeHolder(program, shaderProgramInfo, code);
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}
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shaderPrograms.Add(program);
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|
@ -341,6 +372,14 @@ namespace Ryujinx.Graphics.Gpu.Shader
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|
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task.OnTask(compileTask, (bool _, ShaderCompileTask task) =>
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{
|
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if (task.IsFaulted)
|
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{
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Logger.Warning?.Print(LogClass.Gpu, $"Host shader {key} is corrupted or incompatible, discarding...");
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_cacheManager.RemoveProgram(ref key);
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return true; // Exit early, the decoding step failed.
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}
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// If the host program was rejected by the gpu driver or isn't in cache, try to build from program sources again.
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if (!isHostProgramValid)
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{
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|
@ -537,7 +576,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
|
|||
isShaderCacheReadOnly = _cacheManager.IsReadOnly;
|
||||
|
||||
// Compute hash and prepare data for shader disk cache comparison.
|
||||
shaderCacheEntries = CacheHelper.CreateShaderCacheEntries(channel.MemoryManager, shaderContexts);
|
||||
shaderCacheEntries = CacheHelper.CreateShaderCacheEntries(channel, shaderContexts);
|
||||
programCodeHash = CacheHelper.ComputeGuestHashFromCache(shaderCacheEntries);
|
||||
}
|
||||
|
||||
|
@ -659,7 +698,7 @@ namespace Ryujinx.Graphics.Gpu.Shader
|
|||
isShaderCacheReadOnly = _cacheManager.IsReadOnly;
|
||||
|
||||
// Compute hash and prepare data for shader disk cache comparison.
|
||||
shaderCacheEntries = CacheHelper.CreateShaderCacheEntries(channel.MemoryManager, shaderContexts);
|
||||
shaderCacheEntries = CacheHelper.CreateShaderCacheEntries(channel, shaderContexts);
|
||||
programCodeHash = CacheHelper.ComputeGuestHashFromCache(shaderCacheEntries, tfd);
|
||||
}
|
||||
|
||||
|
|
|
@ -1,5 +1,4 @@
|
|||
using Ryujinx.Graphics.GAL;
|
||||
using System;
|
||||
using System.Threading;
|
||||
using System.Threading.Tasks;
|
||||
|
||||
|
@ -20,6 +19,8 @@ namespace Ryujinx.Graphics.Gpu.Shader
|
|||
private ShaderCompileTaskCallback _action;
|
||||
private AutoResetEvent _taskDoneEvent;
|
||||
|
||||
public bool IsFaulted => _programsTask.IsFaulted;
|
||||
|
||||
/// <summary>
|
||||
/// Create a new shader compile task, with an event to signal whenever a subtask completes.
|
||||
/// </summary>
|
||||
|
|
|
@ -8,10 +8,38 @@ namespace Ryujinx.Graphics.Shader.Decoders
|
|||
public ulong Address { get; set; }
|
||||
public ulong EndAddress { get; set; }
|
||||
|
||||
public Block Next { get; set; }
|
||||
public Block Branch { get; set; }
|
||||
private Block _next;
|
||||
private Block _branch;
|
||||
|
||||
public OpCodeBranchIndir BrIndir { get; set; }
|
||||
public Block Next
|
||||
{
|
||||
get
|
||||
{
|
||||
return _next;
|
||||
}
|
||||
set
|
||||
{
|
||||
_next?.Predecessors.Remove(this);
|
||||
value?.Predecessors.Add(this);
|
||||
_next = value;
|
||||
}
|
||||
}
|
||||
|
||||
public Block Branch
|
||||
{
|
||||
get
|
||||
{
|
||||
return _branch;
|
||||
}
|
||||
set
|
||||
{
|
||||
_branch?.Predecessors.Remove(this);
|
||||
value?.Predecessors.Add(this);
|
||||
_branch = value;
|
||||
}
|
||||
}
|
||||
|
||||
public HashSet<Block> Predecessors { get; }
|
||||
|
||||
public List<OpCode> OpCodes { get; }
|
||||
public List<OpCodePush> PushOpCodes { get; }
|
||||
|
@ -20,6 +48,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
|
|||
{
|
||||
Address = address;
|
||||
|
||||
Predecessors = new HashSet<Block>();
|
||||
|
||||
OpCodes = new List<OpCode>();
|
||||
PushOpCodes = new List<OpCodePush>();
|
||||
}
|
||||
|
|
|
@ -9,8 +9,6 @@ namespace Ryujinx.Graphics.Shader.Decoders
|
|||
{
|
||||
static class Decoder
|
||||
{
|
||||
public const ulong ShaderEndDelimiter = 0xe2400fffff87000f;
|
||||
|
||||
public static Block[][] Decode(IGpuAccessor gpuAccessor, ulong startAddress, out bool hasBindless)
|
||||
{
|
||||
hasBindless = false;
|
||||
|
@ -51,130 +49,139 @@ namespace Ryujinx.Graphics.Shader.Decoders
|
|||
|
||||
GetBlock(funcAddress);
|
||||
|
||||
while (workQueue.TryDequeue(out Block currBlock))
|
||||
bool hasNewTarget;
|
||||
|
||||
do
|
||||
{
|
||||
// Check if the current block is inside another block.
|
||||
if (BinarySearch(blocks, currBlock.Address, out int nBlkIndex))
|
||||
while (workQueue.TryDequeue(out Block currBlock))
|
||||
{
|
||||
Block nBlock = blocks[nBlkIndex];
|
||||
|
||||
if (nBlock.Address == currBlock.Address)
|
||||
// Check if the current block is inside another block.
|
||||
if (BinarySearch(blocks, currBlock.Address, out int nBlkIndex))
|
||||
{
|
||||
throw new InvalidOperationException("Found duplicate block address on the list.");
|
||||
}
|
||||
Block nBlock = blocks[nBlkIndex];
|
||||
|
||||
nBlock.Split(currBlock);
|
||||
blocks.Insert(nBlkIndex + 1, currBlock);
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
// If we have a block after the current one, set the limit address.
|
||||
ulong limitAddress = ulong.MaxValue;
|
||||
|
||||
if (nBlkIndex != blocks.Count)
|
||||
{
|
||||
Block nBlock = blocks[nBlkIndex];
|
||||
|
||||
int nextIndex = nBlkIndex + 1;
|
||||
|
||||
if (nBlock.Address < currBlock.Address && nextIndex < blocks.Count)
|
||||
{
|
||||
limitAddress = blocks[nextIndex].Address;
|
||||
}
|
||||
else if (nBlock.Address > currBlock.Address)
|
||||
{
|
||||
limitAddress = blocks[nBlkIndex].Address;
|
||||
}
|
||||
}
|
||||
|
||||
FillBlock(gpuAccessor, currBlock, limitAddress, startAddress, out bool blockHasBindless);
|
||||
hasBindless |= blockHasBindless;
|
||||
|
||||
if (currBlock.OpCodes.Count != 0)
|
||||
{
|
||||
// We should have blocks for all possible branch targets,
|
||||
// including those from SSY/PBK instructions.
|
||||
foreach (OpCodePush pushOp in currBlock.PushOpCodes)
|
||||
{
|
||||
GetBlock(pushOp.GetAbsoluteAddress());
|
||||
}
|
||||
|
||||
// Set child blocks. "Branch" is the block the branch instruction
|
||||
// points to (when taken), "Next" is the block at the next address,
|
||||
// executed when the branch is not taken. For Unconditional Branches
|
||||
// or end of program, Next is null.
|
||||
OpCode lastOp = currBlock.GetLastOp();
|
||||
|
||||
if (lastOp is OpCodeBranch opBr)
|
||||
{
|
||||
if (lastOp.Emitter == InstEmit.Cal)
|
||||
if (nBlock.Address == currBlock.Address)
|
||||
{
|
||||
EnqueueFunction(opBr.GetAbsoluteAddress());
|
||||
throw new InvalidOperationException("Found duplicate block address on the list.");
|
||||
}
|
||||
else
|
||||
|
||||
nBlock.Split(currBlock);
|
||||
blocks.Insert(nBlkIndex + 1, currBlock);
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
// If we have a block after the current one, set the limit address.
|
||||
ulong limitAddress = ulong.MaxValue;
|
||||
|
||||
if (nBlkIndex != blocks.Count)
|
||||
{
|
||||
Block nBlock = blocks[nBlkIndex];
|
||||
|
||||
int nextIndex = nBlkIndex + 1;
|
||||
|
||||
if (nBlock.Address < currBlock.Address && nextIndex < blocks.Count)
|
||||
{
|
||||
currBlock.Branch = GetBlock(opBr.GetAbsoluteAddress());
|
||||
limitAddress = blocks[nextIndex].Address;
|
||||
}
|
||||
else if (nBlock.Address > currBlock.Address)
|
||||
{
|
||||
limitAddress = blocks[nBlkIndex].Address;
|
||||
}
|
||||
}
|
||||
else if (lastOp is OpCodeBranchIndir opBrIndir)
|
||||
|
||||
FillBlock(gpuAccessor, currBlock, limitAddress, startAddress, out bool blockHasBindless);
|
||||
hasBindless |= blockHasBindless;
|
||||
|
||||
if (currBlock.OpCodes.Count != 0)
|
||||
{
|
||||
// An indirect branch could go anywhere, we don't know the target.
|
||||
// Those instructions are usually used on a switch to jump table
|
||||
// compiler optimization, and in those cases the possible targets
|
||||
// seems to be always right after the BRX itself. We can assume
|
||||
// that the possible targets are all the blocks in-between the
|
||||
// instruction right after the BRX, and the common target that
|
||||
// all the "cases" should eventually jump to, acting as the
|
||||
// switch break.
|
||||
Block firstTarget = GetBlock(currBlock.EndAddress);
|
||||
// We should have blocks for all possible branch targets,
|
||||
// including those from SSY/PBK instructions.
|
||||
foreach (OpCodePush pushOp in currBlock.PushOpCodes)
|
||||
{
|
||||
GetBlock(pushOp.GetAbsoluteAddress());
|
||||
}
|
||||
|
||||
firstTarget.BrIndir = opBrIndir;
|
||||
// Set child blocks. "Branch" is the block the branch instruction
|
||||
// points to (when taken), "Next" is the block at the next address,
|
||||
// executed when the branch is not taken. For Unconditional Branches
|
||||
// or end of program, Next is null.
|
||||
OpCode lastOp = currBlock.GetLastOp();
|
||||
|
||||
opBrIndir.PossibleTargets.Add(firstTarget);
|
||||
if (lastOp is OpCodeBranch opBr)
|
||||
{
|
||||
if (lastOp.Emitter == InstEmit.Cal)
|
||||
{
|
||||
EnqueueFunction(opBr.GetAbsoluteAddress());
|
||||
}
|
||||
else
|
||||
{
|
||||
currBlock.Branch = GetBlock(opBr.GetAbsoluteAddress());
|
||||
}
|
||||
}
|
||||
|
||||
if (!IsUnconditionalBranch(lastOp))
|
||||
{
|
||||
currBlock.Next = GetBlock(currBlock.EndAddress);
|
||||
}
|
||||
}
|
||||
|
||||
if (!IsUnconditionalBranch(lastOp))
|
||||
// Insert the new block on the list (sorted by address).
|
||||
if (blocks.Count != 0)
|
||||
{
|
||||
currBlock.Next = GetBlock(currBlock.EndAddress);
|
||||
Block nBlock = blocks[nBlkIndex];
|
||||
|
||||
blocks.Insert(nBlkIndex + (nBlock.Address < currBlock.Address ? 1 : 0), currBlock);
|
||||
}
|
||||
else
|
||||
{
|
||||
blocks.Add(currBlock);
|
||||
}
|
||||
}
|
||||
|
||||
// Insert the new block on the list (sorted by address).
|
||||
if (blocks.Count != 0)
|
||||
// Propagate SSY/PBK addresses into their uses (SYNC/BRK).
|
||||
foreach (Block block in blocks.Where(x => x.PushOpCodes.Count != 0))
|
||||
{
|
||||
Block nBlock = blocks[nBlkIndex];
|
||||
|
||||
blocks.Insert(nBlkIndex + (nBlock.Address < currBlock.Address ? 1 : 0), currBlock);
|
||||
}
|
||||
else
|
||||
{
|
||||
blocks.Add(currBlock);
|
||||
}
|
||||
|
||||
// Do we have a block after the current one?
|
||||
if (currBlock.BrIndir != null && HasBlockAfter(gpuAccessor, currBlock, startAddress))
|
||||
{
|
||||
bool targetVisited = visited.ContainsKey(currBlock.EndAddress);
|
||||
|
||||
Block possibleTarget = GetBlock(currBlock.EndAddress);
|
||||
|
||||
currBlock.BrIndir.PossibleTargets.Add(possibleTarget);
|
||||
|
||||
if (!targetVisited)
|
||||
for (int pushOpIndex = 0; pushOpIndex < block.PushOpCodes.Count; pushOpIndex++)
|
||||
{
|
||||
possibleTarget.BrIndir = currBlock.BrIndir;
|
||||
PropagatePushOp(visited, block, pushOpIndex);
|
||||
}
|
||||
}
|
||||
|
||||
// Try to find target for BRX (indirect branch) instructions.
|
||||
hasNewTarget = false;
|
||||
|
||||
foreach (Block block in blocks)
|
||||
{
|
||||
if (block.GetLastOp() is OpCodeBranchIndir opBrIndir && opBrIndir.PossibleTargets.Count == 0)
|
||||
{
|
||||
ulong baseOffset = opBrIndir.Address + 8 + (ulong)opBrIndir.Offset;
|
||||
|
||||
// An indirect branch could go anywhere,
|
||||
// try to get the possible target offsets from the constant buffer.
|
||||
(int cbBaseOffset, int cbOffsetsCount) = FindBrxTargetRange(block, opBrIndir.Ra.Index);
|
||||
|
||||
if (cbOffsetsCount != 0)
|
||||
{
|
||||
hasNewTarget = true;
|
||||
}
|
||||
|
||||
for (int i = 0; i < cbOffsetsCount; i++)
|
||||
{
|
||||
uint targetOffset = gpuAccessor.ConstantBuffer1Read(cbBaseOffset + i * 4);
|
||||
Block target = GetBlock(baseOffset + targetOffset);
|
||||
opBrIndir.PossibleTargets.Add(target);
|
||||
target.Predecessors.Add(block);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// If we discovered new branch targets from the BRX instruction,
|
||||
// we need another round of decoding to decode the new blocks.
|
||||
// Additionally, we may have more SSY/PBK targets to propagate,
|
||||
// and new BRX instructions.
|
||||
}
|
||||
|
||||
foreach (Block block in blocks.Where(x => x.PushOpCodes.Count != 0))
|
||||
{
|
||||
for (int pushOpIndex = 0; pushOpIndex < block.PushOpCodes.Count; pushOpIndex++)
|
||||
{
|
||||
PropagatePushOp(visited, block, pushOpIndex);
|
||||
}
|
||||
}
|
||||
while (hasNewTarget);
|
||||
|
||||
funcs.Add(blocks.ToArray());
|
||||
}
|
||||
|
@ -182,19 +189,6 @@ namespace Ryujinx.Graphics.Shader.Decoders
|
|||
return funcs.ToArray();
|
||||
}
|
||||
|
||||
private static bool HasBlockAfter(IGpuAccessor gpuAccessor, Block currBlock, ulong startAdddress)
|
||||
{
|
||||
if (!gpuAccessor.MemoryMapped(startAdddress + currBlock.EndAddress) ||
|
||||
!gpuAccessor.MemoryMapped(startAdddress + currBlock.EndAddress + 7))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
ulong inst = gpuAccessor.MemoryRead<ulong>(startAdddress + currBlock.EndAddress);
|
||||
|
||||
return inst != 0UL && inst != ShaderEndDelimiter;
|
||||
}
|
||||
|
||||
private static bool BinarySearch(List<Block> blocks, ulong address, out int index)
|
||||
{
|
||||
index = 0;
|
||||
|
@ -320,6 +314,115 @@ namespace Ryujinx.Graphics.Shader.Decoders
|
|||
opCode is OpCodeExit;
|
||||
}
|
||||
|
||||
private static (int, int) FindBrxTargetRange(Block block, int brxReg)
|
||||
{
|
||||
// Try to match the following pattern:
|
||||
//
|
||||
// IMNMX.U32 Rx, Rx, UpperBound, PT
|
||||
// SHL Rx, Rx, 0x2
|
||||
// LDC Rx, c[0x1][Rx+BaseOffset]
|
||||
//
|
||||
// Here, Rx is an arbitrary register, "UpperBound" and "BaseOffset" are constants.
|
||||
// The above pattern is assumed to be generated by the compiler before BRX,
|
||||
// as the instruction is usually used to implement jump tables for switch statement optimizations.
|
||||
// On a successful match, "BaseOffset" is the offset in bytes where the jump offsets are
|
||||
// located on the constant buffer, and "UpperBound" is the total number of offsets for the BRX, minus 1.
|
||||
|
||||
HashSet<Block> visited = new HashSet<Block>();
|
||||
|
||||
var ldcLocation = FindFirstRegWrite(visited, new BlockLocation(block, block.OpCodes.Count - 1), brxReg);
|
||||
if (ldcLocation.Block == null || ldcLocation.Block.OpCodes[ldcLocation.Index] is not OpCodeLdc opLdc)
|
||||
{
|
||||
return (0, 0);
|
||||
}
|
||||
|
||||
if (opLdc.Slot != 1 || opLdc.IndexMode != CbIndexMode.Default)
|
||||
{
|
||||
return (0, 0);
|
||||
}
|
||||
|
||||
var shlLocation = FindFirstRegWrite(visited, ldcLocation, opLdc.Ra.Index);
|
||||
if (shlLocation.Block == null || shlLocation.Block.OpCodes[shlLocation.Index] is not OpCodeAluImm opShl)
|
||||
{
|
||||
return (0, 0);
|
||||
}
|
||||
|
||||
if (opShl.Emitter != InstEmit.Shl || opShl.Immediate != 2)
|
||||
{
|
||||
return (0, 0);
|
||||
}
|
||||
|
||||
var imnmxLocation = FindFirstRegWrite(visited, shlLocation, opShl.Ra.Index);
|
||||
if (imnmxLocation.Block == null || imnmxLocation.Block.OpCodes[imnmxLocation.Index] is not OpCodeAluImm opImnmx)
|
||||
{
|
||||
return (0, 0);
|
||||
}
|
||||
|
||||
bool isImnmxS32 = opImnmx.RawOpCode.Extract(48);
|
||||
|
||||
if (opImnmx.Emitter != InstEmit.Imnmx || isImnmxS32 || !opImnmx.Predicate39.IsPT || opImnmx.InvertP)
|
||||
{
|
||||
return (0, 0);
|
||||
}
|
||||
|
||||
return (opLdc.Offset, opImnmx.Immediate + 1);
|
||||
}
|
||||
|
||||
private struct BlockLocation
|
||||
{
|
||||
public Block Block { get; }
|
||||
public int Index { get; }
|
||||
|
||||
public BlockLocation(Block block, int index)
|
||||
{
|
||||
Block = block;
|
||||
Index = index;
|
||||
}
|
||||
}
|
||||
|
||||
private static BlockLocation FindFirstRegWrite(HashSet<Block> visited, BlockLocation location, int regIndex)
|
||||
{
|
||||
Queue<BlockLocation> toVisit = new Queue<BlockLocation>();
|
||||
toVisit.Enqueue(location);
|
||||
visited.Add(location.Block);
|
||||
|
||||
while (toVisit.TryDequeue(out var currentLocation))
|
||||
{
|
||||
Block block = currentLocation.Block;
|
||||
for (int i = currentLocation.Index - 1; i >= 0; i--)
|
||||
{
|
||||
if (WritesToRegister(block.OpCodes[i], regIndex))
|
||||
{
|
||||
return new BlockLocation(block, i);
|
||||
}
|
||||
}
|
||||
|
||||
foreach (Block predecessor in block.Predecessors)
|
||||
{
|
||||
if (visited.Add(predecessor))
|
||||
{
|
||||
toVisit.Enqueue(new BlockLocation(predecessor, predecessor.OpCodes.Count));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return new BlockLocation(null, 0);
|
||||
}
|
||||
|
||||
private static bool WritesToRegister(OpCode opCode, int regIndex)
|
||||
{
|
||||
// Predicate instruction only ever writes to predicate, so we shouldn't check those.
|
||||
if (opCode.Emitter == InstEmit.Fsetp ||
|
||||
opCode.Emitter == InstEmit.Hsetp2 ||
|
||||
opCode.Emitter == InstEmit.Isetp ||
|
||||
opCode.Emitter == InstEmit.R2p)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
return opCode is IOpCodeRd opRd && opRd.Rd.Index == regIndex;
|
||||
}
|
||||
|
||||
private enum MergeType
|
||||
{
|
||||
Brk = 0,
|
||||
|
@ -388,6 +491,8 @@ namespace Ryujinx.Graphics.Shader.Decoders
|
|||
{
|
||||
OpCodePush pushOp = currBlock.PushOpCodes[pushOpIndex];
|
||||
|
||||
Block target = blocks[pushOp.GetAbsoluteAddress()];
|
||||
|
||||
Stack<PathBlockState> workQueue = new Stack<PathBlockState>();
|
||||
|
||||
HashSet<Block> visited = new HashSet<Block>();
|
||||
|
@ -497,10 +602,12 @@ namespace Ryujinx.Graphics.Shader.Decoders
|
|||
if (branchStack.Count == 0)
|
||||
{
|
||||
// If the entire stack was consumed, then the current pop instruction
|
||||
// just consumed the address from out push instruction.
|
||||
op.Targets.Add(pushOp, op.Targets.Count);
|
||||
|
||||
pushOp.PopOps.TryAdd(op, Local());
|
||||
// just consumed the address from our push instruction.
|
||||
if (op.Targets.TryAdd(pushOp, op.Targets.Count))
|
||||
{
|
||||
pushOp.PopOps.Add(op, Local());
|
||||
target.Predecessors.Add(current);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
|
@ -7,6 +7,11 @@
|
|||
// No default log output.
|
||||
}
|
||||
|
||||
uint ConstantBuffer1Read(int offset)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
T MemoryRead<T>(ulong address) where T : unmanaged;
|
||||
|
||||
bool MemoryMapped(ulong address)
|
||||
|
|
|
@ -25,6 +25,12 @@ namespace Ryujinx.Graphics.Shader.Instructions
|
|||
{
|
||||
OpCodeBranchIndir op = (OpCodeBranchIndir)context.CurrOp;
|
||||
|
||||
if (op.PossibleTargets.Count == 0)
|
||||
{
|
||||
context.Config.GpuAccessor.Log($"Failed to find targets for BRX instruction at 0x{op.Address:X}.");
|
||||
return;
|
||||
}
|
||||
|
||||
int offset = (int)op.Address + 8 + op.Offset;
|
||||
|
||||
Operand address = context.IAdd(Register(op.Ra), Const(offset));
|
||||
|
|
Loading…
Reference in a new issue