mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-10-01 12:30:00 +02:00
Review of cpu tests and creation of a class for mixed cpu tests. (#35)
* Update CpuTest.cs * Update CpuTestAlu.cs * Update CpuTestScalar.cs * Update CpuTestSimdMove.cs * Create CpuTestMisc.cs * Update CpuTest.cs * Update CpuTestScalar.cs * Update CpuTest.cs * Update CpuTestAlu.cs * Update CpuTestMisc.cs * Update CpuTestScalar.cs
This commit is contained in:
LDj3SNuD
gdkchan
parent
0ff5ec5cb5
commit
f09a0082bf
5 changed files with 354 additions and 56 deletions
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@ -1,4 +1,4 @@
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using ChocolArm64;
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using ChocolArm64;
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using ChocolArm64.Memory;
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using ChocolArm64.State;
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using NUnit.Framework;
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@ -9,65 +9,93 @@ using System.Threading;
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namespace Ryujinx.Tests.Cpu
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{
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[TestFixture]
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public partial class CpuTest
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public class CpuTest
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{
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IntPtr Ram;
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AMemoryAlloc Allocator;
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AMemory Memory;
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protected long Position { get; private set; }
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private long Size;
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private long EntryPoint;
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private IntPtr Ram;
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private AMemoryAlloc Allocator;
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private AMemory Memory;
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private AThread Thread;
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[SetUp]
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public void Setup()
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{
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Position = 0x0;
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Size = 0x1000;
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EntryPoint = Position;
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Ram = Marshal.AllocHGlobal((IntPtr)AMemoryMgr.RamSize);
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Allocator = new AMemoryAlloc();
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Memory = new AMemory(Ram, Allocator);
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Memory.Manager.MapPhys(0x1000, 0x1000, 2, AMemoryPerm.Read | AMemoryPerm.Write | AMemoryPerm.Execute);
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Memory.Manager.MapPhys(Position, Size, 2, AMemoryPerm.Read | AMemoryPerm.Write | AMemoryPerm.Execute);
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Thread = new AThread(Memory, ThreadPriority.Normal, EntryPoint);
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}
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[TearDown]
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public void Teardown()
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{
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Thread = null;
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Memory = null;
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Allocator = null;
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Marshal.FreeHGlobal(Ram);
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}
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private void Execute(AThread Thread)
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protected void Reset()
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{
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AutoResetEvent Wait = new AutoResetEvent(false);
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Thread.ThreadState.Break += (sender, e) => Thread.StopExecution();
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Thread.WorkFinished += (sender, e) => Wait.Set();
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Wait.Reset();
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Thread.Execute();
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Wait.WaitOne();
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Teardown();
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Setup();
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}
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private AThreadState SingleOpcode(uint Opcode,
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ulong X0 = 0, ulong X1 = 0, ulong X2 = 0,
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AVec V0 = new AVec(), AVec V1 = new AVec(), AVec V2 = new AVec())
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protected void Opcode(uint Opcode)
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{
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Memory.WriteUInt32(0x1000, Opcode);
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Memory.WriteUInt32(0x1004, 0xD4200000); // BRK #0
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Memory.WriteUInt32(0x1008, 0xD65F03C0); // RET
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Thread.Memory.WriteUInt32(Position, Opcode);
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Position += 4;
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}
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AThread Thread = new AThread(Memory, ThreadPriority.Normal, 0x1000);
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protected void SetThreadState(ulong X0 = 0, ulong X1 = 0, ulong X2 = 0,
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AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec))
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{
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Thread.ThreadState.X0 = X0;
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Thread.ThreadState.X1 = X1;
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Thread.ThreadState.X2 = X2;
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Thread.ThreadState.V0 = V0;
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Thread.ThreadState.V1 = V1;
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Thread.ThreadState.V2 = V2;
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Execute(Thread);
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}
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protected void ExecuteOpcodes()
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{
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using (ManualResetEvent Wait = new ManualResetEvent(false))
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{
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Thread.ThreadState.Break += (sender, e) => Thread.StopExecution();
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Thread.WorkFinished += (sender, e) => Wait.Set();
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Thread.Execute();
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Wait.WaitOne();
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}
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}
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protected AThreadState GetThreadState()
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{
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return Thread.ThreadState;
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}
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[Test]
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public void SanityCheck()
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protected AThreadState SingleOpcode(uint Opcode,
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ulong X0 = 0, ulong X1 = 0, ulong X2 = 0,
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AVec V0 = default(AVec), AVec V1 = default(AVec), AVec V2 = default(AVec))
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{
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uint Opcode = 0xD503201F; // NOP
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Assert.AreEqual(SingleOpcode(Opcode, X0: 0).X0, 0);
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Assert.AreEqual(SingleOpcode(Opcode, X0: 1).X0, 1);
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Assert.AreEqual(SingleOpcode(Opcode, X0: 2).X0, 2);
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Assert.AreEqual(SingleOpcode(Opcode, X0: 42).X0, 42);
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this.Opcode(Opcode);
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this.Opcode(0xD4200000); // BRK #0
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this.Opcode(0xD65F03C0); // RET
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SetThreadState(X0, X1, X2, V0, V1, V2);
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ExecuteOpcodes();
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return GetThreadState();
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}
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}
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}
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@ -1,10 +1,9 @@
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using ChocolArm64.State;
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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[TestFixture]
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public partial class CpuTest
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public class CpuTestAlu : CpuTest
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{
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[Test]
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public void Add()
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@ -14,25 +13,17 @@ namespace Ryujinx.Tests.Cpu
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Assert.AreEqual(3, ThreadState.X0);
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}
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[Test]
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public void Ands()
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[TestCase(0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFul, true, false)]
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[TestCase(0xFFFFFFFFu, 0x00000000u, 0x00000000ul, false, true)]
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[TestCase(0x12345678u, 0x7324A993u, 0x12240010ul, false, false)]
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public void Ands(uint A, uint B, ulong Result, bool Negative, bool Zero)
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{
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// ANDS W0, W1, W2
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uint Opcode = 0x6A020020;
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var tests = new[]
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{
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new { W1 = 0xFFFFFFFFul, W2 = 0xFFFFFFFFul, Result = 0xFFFFFFFFul, Negative = true, Zero = false },
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new { W1 = 0xFFFFFFFFul, W2 = 0x00000000ul, Result = 0x00000000ul, Negative = false, Zero = true },
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new { W1 = 0x12345678ul, W2 = 0x7324A993ul, Result = 0x12240010ul, Negative = false, Zero = false },
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};
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foreach (var test in tests)
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{
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AThreadState ThreadState = SingleOpcode(Opcode, X1: test.W1, X2: test.W2);
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Assert.AreEqual(test.Result, ThreadState.X0);
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Assert.AreEqual(test.Negative, ThreadState.Negative);
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Assert.AreEqual(test.Zero, ThreadState.Zero);
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}
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AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B);
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Assert.AreEqual(Result, ThreadState.X0);
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Assert.AreEqual(Negative, ThreadState.Negative);
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Assert.AreEqual(Zero, ThreadState.Zero);
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}
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[Test]
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@ -40,8 +31,14 @@ namespace Ryujinx.Tests.Cpu
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{
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// ORR W0, WZR, #0x01010101
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Assert.AreEqual(0x01010101, SingleOpcode(0x3200C3E0).X0);
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Reset();
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// ORR W1, WZR, #0x00F000F0
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Assert.AreEqual(0x00F000F0, SingleOpcode(0x320C8FE1).X1);
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Reset();
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// ORR W2, WZR, #1
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Assert.AreEqual(0x00000001, SingleOpcode(0x320003E2).X2);
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}
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276
Ryujinx.Tests/Cpu/CpuTestMisc.cs
Normal file
276
Ryujinx.Tests/Cpu/CpuTestMisc.cs
Normal file
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@ -0,0 +1,276 @@
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using ChocolArm64.State;
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using NUnit.Framework;
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namespace Ryujinx.Tests.Cpu
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{
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public class CpuTestMisc : CpuTest
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{
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[TestCase(0ul)]
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[TestCase(1ul)]
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[TestCase(2ul)]
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[TestCase(42ul)]
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public void SanityCheck(ulong A)
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{
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// NOP
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uint Opcode = 0xD503201F;
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AThreadState ThreadState = SingleOpcode(Opcode, X0: A);
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Assert.AreEqual(A, ThreadState.X0);
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}
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[TestCase(0xFFFFFFFDu)] // Roots.
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[TestCase(0x00000005u)]
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public void Misc1(uint A)
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{
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// ((A + 3) * (A - 5)) / ((A + 5) * (A - 3)) = 0
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/*
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ADD W2, W0, 3
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SUB W1, W0, #5
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MUL W2, W2, W1
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ADD W1, W0, 5
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SUB W0, W0, #3
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MUL W0, W1, W0
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SDIV W0, W2, W0
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BRK #0
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RET
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*/
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SetThreadState(X0: A);
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Opcode(0x11000C02);
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Opcode(0x51001401);
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Opcode(0x1B017C42);
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Opcode(0x11001401);
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Opcode(0x51000C00);
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Opcode(0x1B007C20);
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Opcode(0x1AC00C40);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.AreEqual(0, GetThreadState().X0);
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}
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[TestCase(-20f, -5f)] // 18 integer solutions.
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[TestCase(-12f, -6f)]
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[TestCase(-12f, 3f)]
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[TestCase(-8f, -8f)]
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[TestCase(-6f, -12f)]
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[TestCase(-5f, -20f)]
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[TestCase(-4f, 2f)]
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[TestCase(-3f, 12f)]
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[TestCase(-2f, 4f)]
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[TestCase(2f, -4f)]
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[TestCase(3f, -12f)]
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[TestCase(4f, -2f)]
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[TestCase(5f, 20f)]
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[TestCase(6f, 12f)]
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[TestCase(8f, 8f)]
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[TestCase(12f, -3f)]
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[TestCase(12f, 6f)]
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[TestCase(20f, 5f)]
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public void Misc2(float A, float B)
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{
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// 1 / ((1 / A + 1 / B) ^ 2) = 16
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/*
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FMOV S2, 1.0e+0
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FDIV S0, S2, S0
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FDIV S1, S2, S1
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FADD S0, S0, S1
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FDIV S0, S2, S0
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FMUL S0, S0, S0
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BRK #0
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RET
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*/
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SetThreadState(V0: new AVec { S0 = A }, V1: new AVec { S0 = B });
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Opcode(0x1E2E1002);
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Opcode(0x1E201840);
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Opcode(0x1E211841);
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Opcode(0x1E212800);
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Opcode(0x1E201840);
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Opcode(0x1E200800);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.AreEqual(16f, GetThreadState().V0.S0);
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}
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[TestCase(-20d, -5d)] // 18 integer solutions.
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[TestCase(-12d, -6d)]
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[TestCase(-12d, 3d)]
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[TestCase(-8d, -8d)]
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[TestCase(-6d, -12d)]
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[TestCase(-5d, -20d)]
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[TestCase(-4d, 2d)]
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[TestCase(-3d, 12d)]
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[TestCase(-2d, 4d)]
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[TestCase(2d, -4d)]
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[TestCase(3d, -12d)]
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[TestCase(4d, -2d)]
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[TestCase(5d, 20d)]
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[TestCase(6d, 12d)]
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[TestCase(8d, 8d)]
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[TestCase(12d, -3d)]
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[TestCase(12d, 6d)]
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[TestCase(20d, 5d)]
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public void Misc3(double A, double B)
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{
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// 1 / ((1 / A + 1 / B) ^ 2) = 16
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/*
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FMOV D2, 1.0e+0
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FDIV D0, D2, D0
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FDIV D1, D2, D1
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FADD D0, D0, D1
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FDIV D0, D2, D0
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FMUL D0, D0, D0
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BRK #0
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RET
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*/
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SetThreadState(V0: new AVec { D0 = A }, V1: new AVec { D0 = B });
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Opcode(0x1E6E1002);
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Opcode(0x1E601840);
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Opcode(0x1E611841);
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Opcode(0x1E612800);
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Opcode(0x1E601840);
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Opcode(0x1E600800);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.AreEqual(16d, GetThreadState().V0.D0);
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}
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[Test]
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public void MiscR()
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{
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ulong Result = 5;
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/*
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0x0000000000000000: MOV X0, #2
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0x0000000000000004: MOV X1, #3
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0x0000000000000008: ADD X0, X0, X1
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0x000000000000000C: BRK #0
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0x0000000000000010: RET
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*/
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Opcode(0xD2800040);
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Opcode(0xD2800061);
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Opcode(0x8B010000);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.AreEqual(Result, GetThreadState().X0);
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Reset();
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/*
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0x0000000000000000: MOV X0, #3
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0x0000000000000004: MOV X1, #2
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0x0000000000000008: ADD X0, X0, X1
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0x000000000000000C: BRK #0
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0x0000000000000010: RET
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*/
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Opcode(0xD2800060);
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Opcode(0xD2800041);
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Opcode(0x8B010000);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.AreEqual(Result, GetThreadState().X0);
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}
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[Test, Explicit]
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public void Misc5()
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{
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/*
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0x0000000000000000: SUBS X0, X0, #1
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0x0000000000000004: B.NE #0
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0x0000000000000008: BRK #0
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0x000000000000000C: RET
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*/
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SetThreadState(X0: 0x100000000);
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Opcode(0xF1000400);
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Opcode(0x54FFFFE1);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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ExecuteOpcodes();
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Assert.AreEqual(0, GetThreadState().X0);
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Assert.IsTrue(GetThreadState().Zero);
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}
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[Test]
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public void MiscF([Range(0, 92, 1)] int A)
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{
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ulong F_n(uint n)
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{
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ulong a = 0, b = 1, c;
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if (n == 0)
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{
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return a;
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}
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for (uint i = 2; i <= n; i++)
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{
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c = a + b;
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a = b;
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b = c;
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}
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return b;
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}
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/*
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0x0000000000000000: MOV W4, W0
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0x0000000000000004: CBZ W0, #0x3C
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0x0000000000000008: CMP W0, #1
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0x000000000000000C: B.LS #0x48
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0x0000000000000010: MOVZ W2, #0x2
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0x0000000000000014: MOVZ X1, #0x1
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0x0000000000000018: MOVZ X3, #0
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0x000000000000001C: ADD X0, X3, X1
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0x0000000000000020: ADD W2, W2, #1
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0x0000000000000024: MOV X3, X1
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0x0000000000000028: MOV X1, X0
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0x000000000000002C: CMP W4, W2
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0x0000000000000030: B.HS #0x1C
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0x0000000000000034: BRK #0
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0x0000000000000038: RET
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0x000000000000003C: MOVZ X0, #0
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0x0000000000000040: BRK #0
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0x0000000000000044: RET
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0x0000000000000048: MOVZ X0, #0x1
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0x000000000000004C: BRK #0
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0x0000000000000050: RET
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*/
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SetThreadState(X0: (uint)A);
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Opcode(0x2A0003E4);
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Opcode(0x340001C0);
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Opcode(0x7100041F);
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Opcode(0x540001E9);
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Opcode(0x52800042);
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Opcode(0xD2800021);
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Opcode(0xD2800003);
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Opcode(0x8B010060);
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Opcode(0x11000442);
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Opcode(0xAA0103E3);
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Opcode(0xAA0003E1);
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Opcode(0x6B02009F);
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Opcode(0x54FFFF62);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
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Opcode(0xD2800000);
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Opcode(0xD4200000);
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Opcode(0xD65F03C0);
|
||||
Opcode(0xD2800020);
|
||||
Opcode(0xD4200000);
|
||||
Opcode(0xD65F03C0);
|
||||
ExecuteOpcodes();
|
||||
Assert.AreEqual(F_n((uint)A), GetThreadState().X0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -3,8 +3,7 @@ using NUnit.Framework;
|
|||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[TestFixture]
|
||||
public partial class CpuTest
|
||||
public class CpuTestScalar : CpuTest
|
||||
{
|
||||
[TestCase(0x00000000u, 0x80000000u, 0x00000000u)]
|
||||
[TestCase(0x80000000u, 0x00000000u, 0x00000000u)]
|
||||
|
|
@ -15,10 +14,9 @@ namespace Ryujinx.Tests.Cpu
|
|||
[TestCase(0x7F7FFFFFu, 0x807FFFFFu, 0x7F7FFFFFu)]
|
||||
[TestCase(0x7FC00000u, 0x3F800000u, 0x7FC00000u)]
|
||||
[TestCase(0x3F800000u, 0x7FC00000u, 0x7FC00000u)]
|
||||
// NaN tests
|
||||
//[TestCase(0x7F800001u, 0x7FC00042u, 0x7FC00001u)]
|
||||
//[TestCase(0x7FC00042u, 0x7F800001u, 0x7FC00001u)]
|
||||
//[TestCase(0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Au)]
|
||||
[TestCase(0x7F800001u, 0x7FC00042u, 0x7FC00001u, Ignore = "NaN test.")]
|
||||
[TestCase(0x7FC00042u, 0x7F800001u, 0x7FC00001u, Ignore = "NaN test.")]
|
||||
[TestCase(0x7FC0000Au, 0x7FC0000Bu, 0x7FC0000Au, Ignore = "NaN test.")]
|
||||
public void Fmax_S(uint A, uint B, uint Result)
|
||||
{
|
||||
// FMAX S0, S1, S2
|
||||
|
|
|
|||
|
|
@ -3,8 +3,7 @@ using NUnit.Framework;
|
|||
|
||||
namespace Ryujinx.Tests.Cpu
|
||||
{
|
||||
[TestFixture]
|
||||
public partial class CpuTest
|
||||
public class CpuTestSimdMove : CpuTest
|
||||
{
|
||||
[TestCase(0u, 0u, 0x2313221221112010ul, 0x0000000000000000ul)]
|
||||
[TestCase(1u, 0u, 0x2313221221112010ul, 0x2717261625152414ul)]
|
||||
|
|
|
|||
Loading…
Reference in a new issue