LDj3SNuD
e674b37710
Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. ( #468 )
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* Update CpuTest.cs
* Update CpuTestSimd.cs
* Superseded.
* Update AInstEmitSimdCvt.cs
* Update ASoftFloat.cs
* Nit.
* Update PackageReferences.
* Update AInstEmitSimdArithmetic.cs
* Update AVectorHelper.cs
* Update ASoftFloat.cs
* Update ASoftFallback.cs
* Update AThreadState.cs
* Create FPType.cs
* Create FPExc.cs
* Create FPCR.cs
* Create FPSR.cs
* Update ARoundMode.cs
* Update APState.cs
* Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover.
* Nits.
2018-10-23 11:12:45 -03:00
LDj3SNuD
bba9bf97d0
Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. ( #437 )
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* Update CpuTest.cs
* Delete CpuTestSimdCmp.cs
Obsolete.
* Update CpuTestSimdArithmetic.cs
Superseded.
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update ASoftFloat.cs
* Nit.
* Update AOpCodeTable.cs
* Update AOptimizations.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFloat.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFloat.cs
* Update CpuTestSimdReg.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFloat.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-10-05 22:45:59 -03:00
gdkchan
0b52ee6627
Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics ( #405 )
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* Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements
* Remove useless space
* Address PR feedback
* Revert EmitVectorZero32_128 changes
2018-09-26 23:30:21 -03:00
gdkchan
54ed9096bd
Add FMAXP and FMINP (Vector) instructions on the CPU ( #412 )
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* Add FMAXP and FMINP (Vector) instructions on the CPU
* Address PR feedback
2018-09-22 17:26:18 -03:00
LDj3SNuD
c7387be0d2
Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. ( #409 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdShift.cs
* Update CpuTestSimdShImm.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Create CpuTestSimdIns.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
2018-09-17 01:54:05 -03:00
LDj3SNuD
a0c78f7920
Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. ( #407 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdShift.cs
* Update ASoftFallback.cs
* Update AOpCodeSimdShImm.cs
* Update ABitUtils.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Create CpuTestSimdShImm.cs
* Create CpuTestSimdRegElem.cs
* Address PR feedback.
* Nit.
* Nit.
2018-09-08 14:24:29 -03:00
gdkchan
55374ebba0
Zero out bits 63:32 of scalar float operations with SSE intrinsics ( #273 )
2018-08-14 23:54:12 -03:00
LDj3SNuD
02a6fdcd13
Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. Now all saturating methods are on ASoftFallback. ( #334 )
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* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update ASoftFallback.cs
* Update CpuTestAlu.cs
* Update CpuTestAluImm.cs
* Update CpuTestAluRs.cs
* Update CpuTestAluRx.cs
* Update CpuTestBfm.cs
* Update CpuTestCcmpImm.cs
* Update CpuTestCcmpReg.cs
* Update CpuTestCsel.cs
* Update CpuTestMov.cs
* Update CpuTestMul.cs
* Update Ryujinx.Tests.csproj
* Update Ryujinx.csproj
* Update Luea.csproj
* Update Ryujinx.ShaderTools.csproj
* Address PR feedback (further tested).
* Address PR feedback.
2018-08-10 14:27:15 -03:00
LDj3SNuD
5f34353dce
Add SQADD, UQADD, SQSUB, UQSUB, SUQADD, USQADD, SQABS, SQNEG (Scalar, Vector) instructions; add 24 Tests. Most saturation instructions now on ASoftFallback. ( #314 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdArithmetic.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdHelper.cs
* Update ASoftFallback.cs
* Update AInstEmitSimdHelper.cs
* Update ASoftFallback.cs
* Update AInstEmitSimdHelper.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update ASoftFallback.cs
* Update AInstEmitSimdHelper.cs
* Opt. (retest).
2018-08-04 16:58:54 -03:00
LDj3SNuD
fa5545aab8
Implement Ssubw_V and Usubw_V instructions. ( #287 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdMove.cs
* Update AInstEmitSimdCmp.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-07-18 21:06:28 -03:00
LDj3SNuD
063fae50fe
Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. ( #268 )
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* Update CpuTestSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update Instructions.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdMove.cs
* Delete CpuTestSimdMove.cs
2018-07-15 00:53:26 -03:00
gdkchan
514218ab98
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits ( #225 )
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* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions
* Address PR feedback
* Address PR feedback
* Remove another useless temp var
* nit: Alignment
* Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount()
* Fix encodings and move flag bit test out of the loop
2018-07-14 13:13:02 -03:00
Merry
0f8f40486d
ChocolArm64: More accurate implementation of Frecpe & Frecps ( #228 )
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* ChocolArm64: More accurate implementation of Frecpe
* ChocolArm64: Handle infinities and zeros in Frecps
2018-07-08 16:54:47 -03:00
gdkchan
741773910d
Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions ( #200 )
2018-07-03 03:31:48 -03:00
LDj3SNuD
53934e8872
Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. ( #204 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update Instructions.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-06-30 12:40:41 -03:00
gdkchan
bc26aa558a
Add support for the FMLA (by element/scalar) instruction ( #187 )
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* Add support for the FMLA (by element/scalar) instruction
* Fix encoding
2018-06-28 20:51:38 -03:00
LDj3SNuD
8f6387128a
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. ( #183 )
...
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 22:32:29 -03:00
gdkchan
f9f111bc85
Add intrinsics support ( #121 )
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* Initial intrinsics support
* Update tests to work with the new Vector128 type and intrinsics
* Drop SSE4.1 requirement
* Fix copy-paste mistake
2018-05-11 20:10:27 -03:00
LDj3SNuD
7acd0e0122
Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. ( #74 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update CpuTestSimdArithmetic.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
2018-04-08 16:08:57 -03:00
gdkchan
702daf2ff4
[CPU] Fail early when the index/size of the vector is invalid
2018-04-06 15:39:39 -03:00
Merry
39f20d8d1a
Implement Frsqrte_S ( #72 )
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* Implement Frsqrte_S
* Implement Frsqrte_V
* Add Frsqrte_S test
2018-04-05 20:36:19 -03:00
gdkchan
916540ff41
Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction)
2018-03-30 17:37:31 -03:00
gdkchan
88c6160c62
Add MLA (vector by element), fixes some cases of MUL (vector by element)?
2018-03-15 22:36:47 -03:00
gdkchan
553f6c2976
Fix EmitScalarUnaryOpF and add SSRA (vector)
2018-03-10 00:00:31 -03:00
gdkchan
30bcb8da33
Add FRINTM (vector) instruction
2018-03-09 23:41:05 -03:00
gdkchan
be0e4007dc
Add SMLAL (vector), fix EXT instruction
2018-03-06 21:36:49 -03:00
gdkchan
59d1b2ad83
Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
2018-03-05 16:18:37 -03:00
gdkchan
31b35a9645
Add FABD (scalar), ADCS, SBCS instructions, update config with better default control mappings, update readme with the new mappings
2018-02-24 18:47:08 -03:00
emmauss
62b827f474
Split main project into core,graphics and chocolarm4 subproject ( #29 )
2018-02-20 17:09:23 -03:00
