mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-10-01 12:30:00 +02:00
68e15c1a74
* Begin work on A32 SIMD Intrinsics * More instructions, some cleanup. * Intrinsics for Move instructions (zip etc) These pass the existing tests. * Intrinsics for some of Cvt While doing this I noticed that the conversion for int/fp was incorrect in the slow path. I'll fix this in the original repo. * Intrinsics for more Arithmetic instructions. * Intrinsics for Vext * Fix VEXT Intrinsic for double words. * Use InsertPs to move scalar values. * Cleanup, fix VPADD.f32 and VMIN signed integer. * Cleanup, add SSE2 support for scalar insert. Works similarly to the IR scalar insert, but obviously this one works directly on V128. * Minor cleanup. * Enable intrinsic for FP64 to integer conversion. * Address feedback apart from splitting out intrinsic float abs Also: bad VREV encodings as undefined rather than throwing in translation. * Move float abs to helper, fix bug with cvt * Rename opc2 & 3 to match A32 docs, use ArgumentOutOfRangeException appropriately. * Get name of variable at compilation rather than string literal. * Use correct double sign mask.
20 lines
726 B
C#
20 lines
726 B
C#
namespace ARMeilleure.Decoders
|
|
{
|
|
class OpCode32SimdRev : OpCode32SimdCmpZ
|
|
{
|
|
public OpCode32SimdRev(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
|
{
|
|
if (Opc + Size >= 3)
|
|
{
|
|
Instruction = InstDescriptor.Undefined;
|
|
return;
|
|
}
|
|
|
|
// Currently, this instruction is treated as though it's OPCODE is the true size,
|
|
// which lets us deal with reversing vectors on a single element basis (eg. math magic an I64 rather than insert lots of I8s).
|
|
int tempSize = Size;
|
|
Size = 3 - Opc; // Op 0 is 64 bit, 1 is 32 and so on.
|
|
Opc = tempSize;
|
|
}
|
|
}
|
|
}
|