LDj3SNuD 51ea6fa583 Add Smaxv_V, Sminv_V, Umaxv_V, Uminv_V Inst.; add Tests. (#691) ... * Update InstEmitSimdHelper.cs * Update InstEmitSimdArithmetic.cs * Update OpCodeTable.cs * Update CpuTestSimd.cs		2019-05-29 21:29:24 -03:00
..
Decoders	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
Events	Optimize address translation and write tracking on the MMU (#571)	2019-02-24 18:24:35 +11:00
Instructions	Add Smaxv_V, Sminv_V, Umaxv_V, Uminv_V Inst.; add Tests. (#691)	2019-05-29 21:29:24 -03:00
IntermediateRepresentation	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
Memory	Optimize address translation and write tracking on the MMU (#571)	2019-02-24 18:24:35 +11:00
State	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
Translation	Refactoring and optimization on CPU translation (#661)	2019-04-26 14:55:12 +10:00
ChocolArm64.csproj	Built in profiling (#567)	2019-04-26 14:53:10 +10:00
CpuThread.cs	ARM exclusive monitor and multicore fixes (#589)	2019-02-19 10:52:06 +11:00
OpCodeTable.cs	Add Smaxv_V, Sminv_V, Umaxv_V, Uminv_V Inst.; add Tests. (#691)	2019-05-29 21:29:24 -03:00
Optimizations.cs	Misc. CPU optimizations (#575)	2019-02-28 13:03:31 +11:00