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ChocolArm64: More accurate implementation of Frecpe & Frecps (#228)
* ChocolArm64: More accurate implementation of Frecpe * ChocolArm64: Handle infinities and zeros in Frecps
This commit is contained in:
Merry
gdkchan
parent
6479c3e484
commit
0f8f40486d
4 changed files with 170 additions and 109 deletions
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@ -641,106 +641,34 @@ namespace ChocolArm64.Instruction
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public static void Frecpe_S(AILEmitterCtx Context)
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{
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EmitFrecpe(Context, 0, Scalar: true);
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EmitScalarUnaryOpF(Context, () =>
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{
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EmitUnarySoftFloatCall(Context, nameof(ASoftFloat.RecipEstimate));
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});
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}
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public static void Frecpe_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < Bytes >> SizeF + 2; Index++)
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EmitVectorUnaryOpF(Context, () =>
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{
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EmitFrecpe(Context, Index, Scalar: false);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitFrecpe(AILEmitterCtx Context, int Index, bool Scalar)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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if (SizeF == 0)
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{
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Context.EmitLdc_R4(1);
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}
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else /* if (SizeF == 1) */
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{
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Context.EmitLdc_R8(1);
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}
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EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
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Context.Emit(OpCodes.Div);
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if (Scalar)
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{
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EmitVectorZeroAll(Context, Op.Rd);
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}
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EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
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EmitUnarySoftFloatCall(Context, nameof(ASoftFloat.RecipEstimate));
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});
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}
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public static void Frecps_S(AILEmitterCtx Context)
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{
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EmitFrecps(Context, 0, Scalar: true);
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EmitScalarBinaryOpF(Context, () =>
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{
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EmitBinarySoftFloatCall(Context, nameof(ASoftFloat.RecipStep));
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});
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}
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public static void Frecps_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < Bytes >> SizeF + 2; Index++)
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EmitVectorBinaryOpF(Context, () =>
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{
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EmitFrecps(Context, Index, Scalar: false);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitFrecps(AILEmitterCtx Context, int Index, bool Scalar)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int SizeF = Op.Size & 1;
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if (SizeF == 0)
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{
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Context.EmitLdc_R4(2);
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}
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else /* if (SizeF == 1) */
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{
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Context.EmitLdc_R8(2);
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}
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EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
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EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
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Context.Emit(OpCodes.Mul);
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Context.Emit(OpCodes.Sub);
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if (Scalar)
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{
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EmitVectorZeroAll(Context, Op.Rd);
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}
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EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
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EmitBinarySoftFloatCall(Context, nameof(ASoftFloat.RecipStep));
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});
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}
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public static void Frinta_S(AILEmitterCtx Context)
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@ -253,6 +253,26 @@ namespace ChocolArm64.Instruction
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Context.EmitCall(MthdInfo);
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}
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public static void EmitBinarySoftFloatCall(AILEmitterCtx Context, string Name)
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{
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IAOpCodeSimd Op = (IAOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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MethodInfo MthdInfo;
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if (SizeF == 0)
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{
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MthdInfo = typeof(ASoftFloat).GetMethod(Name, new Type[] { typeof(float), typeof(float) });
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}
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else /* if (SizeF == 1) */
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{
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MthdInfo = typeof(ASoftFloat).GetMethod(Name, new Type[] { typeof(double), typeof(double) });
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}
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Context.EmitCall(MthdInfo);
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}
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public static void EmitScalarBinaryOpByElemF(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdRegElemF Op = (AOpCodeSimdRegElemF)Context.CurrOp;
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@ -7,8 +7,10 @@ namespace ChocolArm64.Instruction
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static ASoftFloat()
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{
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InvSqrtEstimateTable = BuildInvSqrtEstimateTable();
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RecipEstimateTable = BuildRecipEstimateTable();
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}
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private static readonly byte[] RecipEstimateTable;
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private static readonly byte[] InvSqrtEstimateTable;
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private static byte[] BuildInvSqrtEstimateTable()
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@ -38,6 +40,22 @@ namespace ChocolArm64.Instruction
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return Table;
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}
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private static byte[] BuildRecipEstimateTable()
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{
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byte[] Table = new byte[256];
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for (ulong index = 0; index < 256; index++)
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{
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ulong a = index | 0x100;
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a = (a << 1) + 1;
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ulong b = 0x80000 / a;
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b = (b + 1) >> 1;
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Table[index] = (byte)(b & 0xFF);
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}
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return Table;
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}
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public static float InvSqrtEstimate(float x)
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{
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return (float)InvSqrtEstimate((double)x);
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@ -105,5 +123,107 @@ namespace ChocolArm64.Instruction
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ulong result = x_sign | (result_exp << 52) | fraction;
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return BitConverter.Int64BitsToDouble((long)result);
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}
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public static float RecipEstimate(float x)
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{
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return (float)RecipEstimate((double)x);
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}
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public static double RecipEstimate(double x)
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{
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ulong x_bits = (ulong)BitConverter.DoubleToInt64Bits(x);
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ulong x_sign = x_bits & 0x8000000000000000;
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ulong x_exp = (x_bits >> 52) & 0x7FF;
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ulong scaled = x_bits & ((1ul << 52) - 1);
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if (x_exp >= 2045)
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{
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if (x_exp == 0x7ff && scaled != 0)
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{
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// NaN
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return BitConverter.Int64BitsToDouble((long)(x_bits | 0x0008000000000000));
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}
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// Infinity, or Out of range -> Zero
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return BitConverter.Int64BitsToDouble((long)x_sign);
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}
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if (x_exp == 0)
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{
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if (scaled == 0)
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{
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// Zero -> Infinity
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return BitConverter.Int64BitsToDouble((long)(x_sign | 0x7ff0000000000000));
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}
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// Denormal
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if ((scaled & (1ul << 51)) == 0)
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{
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x_exp = ~0ul;
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scaled <<= 2;
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}
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else
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{
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scaled <<= 1;
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}
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}
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scaled >>= 44;
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scaled &= 0xFF;
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ulong result_exp = (2045 - x_exp) & 0x7FF;
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ulong estimate = (ulong)RecipEstimateTable[scaled];
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ulong fraction = estimate << 44;
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if (result_exp == 0)
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{
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fraction >>= 1;
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fraction |= 1ul << 51;
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}
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else if (result_exp == 0x7FF)
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{
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result_exp = 0;
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fraction >>= 2;
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fraction |= 1ul << 50;
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}
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ulong result = x_sign | (result_exp << 52) | fraction;
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return BitConverter.Int64BitsToDouble((long)result);
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}
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public static float RecipStep(float op1, float op2)
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{
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return (float)RecipStep((double)op1, (double)op2);
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}
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public static double RecipStep(double op1, double op2)
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{
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op1 = -op1;
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ulong op1_bits = (ulong)BitConverter.DoubleToInt64Bits(op1);
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ulong op2_bits = (ulong)BitConverter.DoubleToInt64Bits(op2);
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ulong op1_sign = op1_bits & 0x8000000000000000;
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ulong op2_sign = op2_bits & 0x8000000000000000;
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ulong op1_other = op1_bits & 0x7FFFFFFFFFFFFFFF;
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ulong op2_other = op2_bits & 0x7FFFFFFFFFFFFFFF;
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bool inf1 = op1_other == 0x7ff0000000000000;
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bool inf2 = op2_other == 0x7ff0000000000000;
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bool zero1 = op1_other == 0;
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bool zero2 = op2_other == 0;
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if ((inf1 && zero2) || (zero1 && inf2))
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{
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return 2.0;
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}
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else if (inf1 || inf2)
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{
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// Infinity
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return BitConverter.Int64BitsToDouble((long)(0x7ff0000000000000 | (op1_sign ^ op2_sign)));
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}
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return 2.0 + op1 * op2;
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}
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}
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}
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@ -163,26 +163,18 @@ namespace Ryujinx.Tests.Cpu
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Assert.That(Sse41.Extract(ThreadState.V6, (byte)0), Is.EqualTo(A * B));
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}
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[Test, Description("FRECPE D0, D1")]
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public void Frecpe_S([Random(100)] double A)
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[TestCase(0x00000000u, 0x7F800000u)]
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[TestCase(0x80000000u, 0xFF800000u)]
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[TestCase(0x00FFF000u, 0x7E000000u)]
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[TestCase(0x41200000u, 0x3DCC8000u)]
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[TestCase(0xC1200000u, 0xBDCC8000u)]
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[TestCase(0x001FFFFFu, 0x7F800000u)]
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[TestCase(0x007FF000u, 0x7E800000u)]
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public void Frecpe_S(uint A, uint Result)
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{
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AThreadState ThreadState = SingleOpcode(0x5EE1D820, V1: MakeVectorE0(A));
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Assert.That(VectorExtractDouble(ThreadState.V0, 0), Is.EqualTo(1 / A));
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}
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[Test, Description("FRECPE V2.4S, V0.4S")]
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public void Frecpe_V([Random(100)] float A)
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{
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AThreadState ThreadState = SingleOpcode(0x4EA1D802, V0: Sse.SetAllVector128(A));
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Assert.Multiple(() =>
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{
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Assert.That(Sse41.Extract(ThreadState.V2, (byte)0), Is.EqualTo(1 / A));
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Assert.That(Sse41.Extract(ThreadState.V2, (byte)1), Is.EqualTo(1 / A));
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Assert.That(Sse41.Extract(ThreadState.V2, (byte)2), Is.EqualTo(1 / A));
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Assert.That(Sse41.Extract(ThreadState.V2, (byte)3), Is.EqualTo(1 / A));
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});
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(0x5EA1D820, V1: V1);
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Assert.AreEqual(Result, GetVectorE0(ThreadState.V0));
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}
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[Test, Description("FRECPS D0, D1, D2")]
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@ -202,12 +194,13 @@ namespace Ryujinx.Tests.Cpu
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V2: Sse.SetAllVector128(A),
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V0: Sse.SetAllVector128(B));
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float Result = (float)(2 - ((double)A * (double)B));
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Assert.Multiple(() =>
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{
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)0), Is.EqualTo(2 - (A * B)));
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)1), Is.EqualTo(2 - (A * B)));
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)2), Is.EqualTo(2 - (A * B)));
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(2 - (A * B)));
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)0), Is.EqualTo(Result));
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)1), Is.EqualTo(Result));
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)2), Is.EqualTo(Result));
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Assert.That(Sse41.Extract(ThreadState.V4, (byte)3), Is.EqualTo(Result));
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});
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}
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