1
0
Fork 0
mirror of https://github.com/Ryujinx/Ryujinx.git synced 2024-10-01 12:30:00 +02:00
Commit graph

13 commits

Author SHA1 Message Date
gdkchan
3777fb44cf Allow to enable/disable memory checks even on release mode through the flag, return error for invalid addresses on SvcMap*Memory svcs, do not return error on SvcQueryMemory (instead, return reserved for the end of the address space), other minor tweaks 2018-03-10 20:39:16 -03:00
gdkchan
5912bd2beb Disable memory checks by default, even on debug, move ram memory allocation inside the CPU, since the size if fixed anyway, better heap region size 2018-03-09 23:12:57 -03:00
MS-DOS1999
c9ef25681d Add Frintx_S, ASRV test, update ADCS, use Assert.Multiple and indent (#44)
* add 'ADC 32bit and Overflow' test

* Add WZR/WSP tests

* fix ADC and ADDS

* add ADCS test

* add SBCS test

* indent my code and delete comment

* '/' <- i hate you x)

* remove spacebar char

* remove false tab

* add frintx_S test

* update frintx_S test

* add ASRV test

* fix new line

* fix PR

* fix indent
2018-03-05 09:21:19 -03:00
gdkchan
f876bd2a80 Change SvcGetInfo 5 to return actual heap size, remove AMemoryAlloc since it is no longer needed with direct memory access, move some memory management logic out of AMemoryMgr, change default virtual filesystem path to AppData 2018-02-27 20:45:07 -03:00
gdkchan
950011c90f Added initial support for function names from symbol table on the cpu with tracing, fix wrong ImageEnd on executables with MOD0, fix issue on the CPU on input elimination for instruction with more than one register store 2018-02-25 22:14:58 -03:00
MS-DOS1999
a4ff0d3484 Update ADC test, add WZR/WSP, ADCS, SBCS test (#37)
* add 'ADC 32bit and Overflow' test

* Add WZR/WSP tests

* fix ADC and ADDS

* add ADCS test

* add SBCS test

* indent my code and delete comment

* '/' <- i hate you x)

* remove spacebar char

* remove false tab
2018-02-24 22:50:58 -03:00
MS-DOS1999
eafc58c9f2 Add flags parameters in singleOpcode function, and add ADC Test (#36)
* Add flags parameters in singleOpcode function, and add ADC Test

* Update CpuTestAlu.cs

* Update CpuTestAlu.cs

* Update CpuTestAlu.cs

* Update CpuTestAlu.cs
2018-02-23 11:53:32 -03:00
LDj3SNuD
f09a0082bf Review of cpu tests and creation of a class for mixed cpu tests. (#35)
* Update CpuTest.cs

* Update CpuTestAlu.cs

* Update CpuTestScalar.cs

* Update CpuTestSimdMove.cs

* Create CpuTestMisc.cs

* Update CpuTest.cs

* Update CpuTestScalar.cs

* Update CpuTest.cs

* Update CpuTestAlu.cs

* Update CpuTestMisc.cs

* Update CpuTestScalar.cs
2018-02-23 09:29:20 -03:00
gdkchan
3696255457 Add ChocolArm64 reference to Ryujinx.Tests 2018-02-20 17:19:00 -03:00
Merry
1039797c30 Implement Zip1, Zip2 (#25) 2018-02-20 07:41:55 -03:00
Merry
8df0b62fe0 Tests: Add Fmax_S test (#23) 2018-02-19 01:17:26 -03:00
gdkchan
f35d286c8d Rename ARegisters to AThreadState 2018-02-18 16:28:07 -03:00
Merry
1bfe6a9c22 Add some tests (#18)
* Add tests

* Add some simple Alu instruction tests

* travis: Run tests

* CpuTest: Add TearDown
2018-02-15 21:04:38 -03:00